📄 neptune_frame_buffer.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :neptune_frame_buffer.h
//
// Date of Module Modification:12/17/03
// Date of Generation :3/18/04
//
//
//========================================================================
#ifndef _FRAME_BUFFER__H
#define _FRAME_BUFFER__H
//this code not generated
#include "global_types.h"
#include "mapping.h"
//4 FB_PU_CONTROL_CLK_FREE When set to one the memory clock is free running. When cleared the clock auto-gating is enabled for power consumption savings. 1
//3 FB_PU_CONTROL_FBPU_SEC When set to one this bit locks the FBPU register access when the device is not in secure mode 0
//2 FB_PU_CONTROL_START_RESET Auto-clear bit.When set to 1, the memory bank configured in the MEMX_RESET register bits is erased.
//1 FB_PU_CONTROL_MEM_RESET When set to 1 the Memory bank will be erased automatically on a reset event or a start reset command R/W(secure mode)1
//0 FB_PU_CONTROL_MEM_PROT Protection control register0: The protection is disabled.1: The memory bank can be accessed according to the conditions described in table 1 R/W(secure mode) 0
//
//1 FB_PU_STATUS_RESET When High this bit indicates a memory bank is being erased and the frame buffer cannot be accessed in the meanwhile. Read only1
//0 FB_PU_STATUS_IA_MEM Memory illegal access status register.0: no violation.1: An access violation occurred on the memory bank R/Clear 0
#define FB_RAM_BASE_ADDR 0x20000000
#define FB_PU_BASE_ADDR 0x20008000
#define FB_PU_STATUS_OFFSET 4
#define FB_PU_CONTROL_OFFSET 0
#define FB_PU_STATUS_REG REG32(FB_PU_BASE_ADDR+FB_PU_STATUS_OFFSET )
#define FB_PU_CONTROL_REG REG32(FB_PU_BASE_ADDR+FB_PU_CONTROL_OFFSET )
#define FB_PU_STATUS_RESET_MASK 0x00000002
#define FB_PU_STATUS_IA_MEM_MASK 0x00000001
#define FB_PU_CONTROL_CLK_FREE_MASK 0x00000010
#define FB_PU_CONTROL_FBPU_SEC_MASK 0x00000008
#define FB_PU_CONTROL_START_RESET_MASK 0x00000004
#define FB_PU_CONTROL_MEM_RESET_MASK 0x00000002
#define FB_PU_CONTROL_MEM_PROT_MASK 0x00000001
#define FB_RAM(ADDR) REG32(FB_RAM_BASE_ADDR+(ADDR<<2) )
#define FB_PU_CONTROL_REG_RESET_VALUE 0x00000012
#define FB_PU_STATUS_REG_RESET_VALUE 0x00000000 //although bit 1 is 0 this test will be called after reset thus after the memory has already been erased
BOOL FB_CurrentlyResetting(void) ;
void FB_EnableProtection(void) ;
void FB_DisableProtection(void) ;
void FB_EnableMemoryReset(void) ;
void FB_DisableMemoryReset(void) ;
void FB_StartMemoryReset(void) ;
void FB_LockFBPUregisters(void) ;
UWORD16 FB_TestResetValues(void) ;
BOOL FB_ViolationReported(void) ;
void FB_ClearIllegalAccessFlag(void) ;
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define coeff8_arm 1
#define coeff16_arm 1
#define coeff32_arm 1
//-------------------
#define FRAME_BUFFER_FRAME_BUFFER_MEMORY_OFFSET 0x0
#define FRAME_BUFFER_FBPU_CONTROL_OFFSET 0x8000
#define FRAME_BUFFER_FBPU_STATUS_OFFSET 0x8004
//FRAME_BUFFER_FRAME_BUFFER_MEMORY
//-------------------
#define FRAME_BUFFER_FRAME_BUFFER_MEMORY_8_0 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FRAME_BUFFER_MEMORY_OFFSET*coeff8_arm+0)
#define FRAME_BUFFER_FRAME_BUFFER_MEMORY_8_1 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FRAME_BUFFER_MEMORY_OFFSET*coeff8_arm+1)
#define FRAME_BUFFER_FRAME_BUFFER_MEMORY_8_2 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FRAME_BUFFER_MEMORY_OFFSET*coeff8_arm+2)
#define FRAME_BUFFER_FRAME_BUFFER_MEMORY_8_3 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FRAME_BUFFER_MEMORY_OFFSET*coeff8_arm+3)
#define FRAME_BUFFER_FRAME_BUFFER_MEMORY_16_0 REG16(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FRAME_BUFFER_MEMORY_OFFSET*coeff16_arm+0)
#define FRAME_BUFFER_FRAME_BUFFER_MEMORY_16_2 REG16(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FRAME_BUFFER_MEMORY_OFFSET*coeff16_arm+2)
#define FRAME_BUFFER_FRAME_BUFFER_MEMORY_32 REG32(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FRAME_BUFFER_MEMORY_OFFSET*coeff32_arm)
//FRAME_BUFFER_FBPU_CONTROL
//-------------------
#define FRAME_BUFFER_FBPU_CONTROL_8_0 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_CONTROL_OFFSET*coeff8_arm+0)
#define FRAME_BUFFER_FBPU_CONTROL_8_0_CLK_FREE_POS 4
#define FRAME_BUFFER_FBPU_CONTROL_8_0_CLK_FREE_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_0_CLK_FREE_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_0_FBPU_SEC_POS 3
#define FRAME_BUFFER_FBPU_CONTROL_8_0_FBPU_SEC_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_0_FBPU_SEC_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_0_START_RESET_POS 2
#define FRAME_BUFFER_FBPU_CONTROL_8_0_START_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_0_START_RESET_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_0_MEM_RESET_POS 1
#define FRAME_BUFFER_FBPU_CONTROL_8_0_MEM_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_0_MEM_RESET_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_0_MEM_PROT_POS 0
#define FRAME_BUFFER_FBPU_CONTROL_8_0_MEM_PROT_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_0_MEM_PROT_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_1 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_CONTROL_OFFSET*coeff8_arm+1)
#define FRAME_BUFFER_FBPU_CONTROL_8_1_CLK_FREE_POS 4
#define FRAME_BUFFER_FBPU_CONTROL_8_1_CLK_FREE_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_1_CLK_FREE_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_1_FBPU_SEC_POS 3
#define FRAME_BUFFER_FBPU_CONTROL_8_1_FBPU_SEC_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_1_FBPU_SEC_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_1_START_RESET_POS 2
#define FRAME_BUFFER_FBPU_CONTROL_8_1_START_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_1_START_RESET_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_1_MEM_RESET_POS 1
#define FRAME_BUFFER_FBPU_CONTROL_8_1_MEM_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_1_MEM_RESET_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_1_MEM_PROT_POS 0
#define FRAME_BUFFER_FBPU_CONTROL_8_1_MEM_PROT_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_1_MEM_PROT_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_2 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_CONTROL_OFFSET*coeff8_arm+2)
#define FRAME_BUFFER_FBPU_CONTROL_8_2_CLK_FREE_POS 4
#define FRAME_BUFFER_FBPU_CONTROL_8_2_CLK_FREE_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_2_CLK_FREE_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_2_FBPU_SEC_POS 3
#define FRAME_BUFFER_FBPU_CONTROL_8_2_FBPU_SEC_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_2_FBPU_SEC_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_2_START_RESET_POS 2
#define FRAME_BUFFER_FBPU_CONTROL_8_2_START_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_2_START_RESET_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_2_MEM_RESET_POS 1
#define FRAME_BUFFER_FBPU_CONTROL_8_2_MEM_RESET_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_2_MEM_RESET_RES_VAL 0x1
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_2_MEM_PROT_POS 0
#define FRAME_BUFFER_FBPU_CONTROL_8_2_MEM_PROT_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_2_MEM_PROT_RES_VAL 0x0
//R/W
#define FRAME_BUFFER_FBPU_CONTROL_8_3 REG8(FRAME_BUFFER_BASE_ADDR_ARM+FRAME_BUFFER_FBPU_CONTROL_OFFSET*coeff8_arm+3)
#define FRAME_BUFFER_FBPU_CONTROL_8_3_CLK_FREE_POS 4
#define FRAME_BUFFER_FBPU_CONTROL_8_3_CLK_FREE_NUMB 1
#define FRAME_BUFFER_FBPU_CONTROL_8_3_CLK_FREE_RES_VAL 0x1
//R/W
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