📄 uwire.h
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#define UWIRE_CSR_REG_RESET_MASK 0xf000
#define UWIRE_SR1_REG_RESET_MASK 0x0104
#define UWIRE_SR2_REG_RESET_MASK 0x0104
#define UWIRE_SR3_REG_RESET_MASK 0x0007
#define UWIRE_SR4_REG_RESET_MASK 0x0001
#define UWIRE_SR5_REG_RESET_MASK 0x000F
#define UWIRE_CSR_CS_CMD_RESET_VALUE 0x0000
#define UWIRE_CSR_START_RESET_VALUE 0x0000
#define UWIRE_CSR_CSRB_RESET_VALUE 0x0000
#define UWIRE_CSR_RDRB_RESET_VALUE 0x0000
#define UWIRE_SR1_CS0CS_LVL_MASK 0x0004
#define UWIRE_SR1_CS1CS_LVL_MASK 0x1000
#define UWIRE_SR2_CS2CS_LVL_MASK 0x0004
#define UWIRE_SR2_CS3CS_LVL_MASK 0x1000
#define UWIRE_SR1_CS0CS_LVL_RESET_VALUE 0x0000
#define UWIRE_SR1_CS1CS_LVL_RESET_VALUE 0x0000
#define UWIRE_SR2_CS2CS_LVL_RESET_VALUE 0x0000
#define UWIRE_SR2_CS3CS_LVL_RESET_VALUE 0x0000
#define UWIRE_EEPROM_MASK 0x3f // EEPROM mask in Setup register
//Control & Status Register Mask
#define UWIRE_CSR_ERASE_MASK 0x3fff // to erase the Control register
#define UWIRE_CSR_NB_BITS_RD_WR_MASK 0x03ff // read and write lengths in CSR
#define UWIRE_CSR_CS_CMD_MASK 0x1000 // CS_CMD bit of the Control register
#define UWIRE_CSR_START_MASK 0x2000 // start bit of the Control register
#define UWIRE_CSR_CSRB_MASK 0x4000 // CSRB bit of the Control register
#define UWIRE_CSR_RDRB_MASK 0x8000 // RDRB bit of the Control register
//--------------------------------
//Setup Register (SR3) Mask
//--------------------------------
//SR3 register mask
#define UWIRE_SR3_MASK 0x0007
//To switch on the clock if 1
#define UWIRE_SR3_CLK_ENABLE_MASK 0x0001
#define UWIRE_SR3_CK_FREQ_MASK 0x0006
#define UWIRE_SR3_CK_FREQ_RESET_VALUE 0x0000
//Default value on reset
#define UWIRE_SR3_CLK_ENABLE_RESET_VALUE 0x0000
//--------------------------------
//Setup Register (SR4) Mask
//--------------------------------
//SR5 register mask
#define UWIRE_SR4_MASK 0x0001
//--------------------------------
//Setup Register (SR5) Mask
//--------------------------------
//SR5 register mask
#define UWIRE_SR5_MASK 0x000F
#define UWIRE_SR5_DMA_TX_MASK 0x0001
#define UWIRE_SR5_IT_MASK 0x0002
#define UWIRE_SR5_AUTO_TX_MASK 0x0004
#define UWIRE_SR5_CS_TOGGLE_MASK 0x0008
/*//Default value on reset
#define UWIRE_SR5_DMA_TX_RESET_VALUE 0x0000
#define UWIRE_SR5_IT_RESET_VALUE 0x0000
#define UWIRE_SR5_AUTO_TX_RESET_VALUE 0x0000
#define UWIRE_SR5_CS_TOGGLE_RESET_VALUE 0x0000*/
// Control Status Register
//=========================
//Reset values / Set Values
#define UWIRE_CSR_NBBITSRD_SET_VAL 0x0
#define UWIRE_CSR_NBBITSWR_SET_VAL 0x0
#define UWIRE_CSR_INDEX_SET_VAL 0x0
#define CS_CMD_RES_VAL 0x0
#define START_RES_VAL 0x0
#define CSRB_RES_VAL 0x0
#define RDRB_RES_VAL 0x0
//Pos values
#define UWIRE_CSR_NBBITSRD_POS 0x0
#define UWIRE_CSR_NBBITSWR_POS 0x5
//#define UWIRE_CSR_INDEX_POS 0xA
#define CS_CMD_POS 0xC
#define START_POS 0xD
#define CSRB_POS 0xE
#define RDRB_POS 0xF
//Width values
#define UWIRE_CSR_NBBITSRD_NUMB 0x5
#define UWIRE_CSR_NBBITSWR_NUMB 0x5
//#define UWIRE_CSR_INDEX_NUMB 0x2
#define CS_CMD_NUMB 1
#define START_NUMB 1
#define CSRB_NUMB 1
#define RDRB_NUMB 1
// Setup Register 1
//==================
//Reset values
#define CS0_EDGE_RD_SET_VAL 0x0
#define CS0_EDGE_WR_SET_VAL 0x0
#define CS0_FRQ_SET_VAL 0x0
#define CS0_CHK_SET_VAL 0x0
#define CS1_EDGE_RD_SET_VAL 0x0
#define CS1_EDGE_WR_SET_VAL 0x0
#define CS1_FRQ_SET_VAL 0x0
#define CS1_CHK_SET_VAL 0x0
#define CS0CS_LVL_RES_VAL 0x0
#define CS1CS_LVL_RES_VAL 0x0
//Pos values
#define CS0_EDGE_RD_POS 0x0
#define CS0_EDGE_WR_POS 0x1
#define CS0CS_LVL_POS 0x2
#define CS0_FRQ_POS 0x3
#define CS0_CHK_POS 0x5
#define CS1_EDGE_RD_POS 0x6
#define CS1_EDGE_WR_POS 0x7
#define CS1CS_LVL_POS 0x8
#define CS1_FRQ_POS 0x9
#define CS1_CHK_POS 0xB
//Width values
#define CS0_EDGE_RD_NUMB 1
#define CS0_EDGE_WR_NUMB 1
#define CS0CS_LVL_NUMB 1
#define CS0_FRQ_NUMB 2
#define CS0_CHK_NUMB 1
#define CS1_EDGE_RD_NUMB 1
#define CS1_EDGE_WR_NUMB 1
#define CS1CS_LVL_NUMB 1
#define CS1_FRQ_NUMB 2
#define CS1_CHK_NUMB 1
// Setup Register 1 and 2
//========================
#define FALLING_EDGE_READ 0x0
#define RISING_EDGE_READ 0x1
#define FALLING_EDGE_WRITE 0x0
#define RISING_EDGE_WRITE 0x1
#define LEVEL_ZERO 0x0
#define LEVEL_ONE 0x1
#define F_INT_OVER_2 0x0
#define F_INT_OVER_4 0x1
#define F_INT_OVER_8 0x2
#define UNDEFINED 0x3
#define CHECK_DEVICE 0x0
#define NO_CHECK_DEVICE 0x1
// Setup Register 2
//==================
//Reset values
#define CS2_EDGE_RD_SET_VAL 0x0
#define CS2_EDGE_WR_SET_VAL 0x0
#define CS2_FRQ_SET_VAL 0x0
#define CS2_CHK_SET_VAL 0x0
#define CS3_EDGE_RD_SET_VAL 0x0
#define CS3_EDGE_WR_SET_VAL 0x0
#define CS3_FRQ_SET_VAL 0x0
#define CS3_CHK_SET_VAL 0x0
#define CS2CS_LVL_RES_VAL 0x0
#define CS3CS_LVL_RES_VAL 0x0
//Pos values
#define CS2_EDGE_RD_POS 0x0
#define CS2_EDGE_WR_POS 0x1
#define CS2CS_LVL_POS 0x2
#define CS2_FRQ_POS 0x3
#define CS2_CHK_POS 0x5
#define CS3_EDGE_RD_POS 0x6
#define CS3_EDGE_WR_POS 0x7
#define CS3CS_LVL_POS 0x8
#define CS3_FRQ_POS 0x9
#define CS3_CHK_POS 0xB
//Width values
#define CS2_EDGE_RD_NUMB 1
#define CS2_EDGE_WR_NUMB 1
#define CS2CS_LVL_NUMB 1
#define CS2_FRQ_NUMB 2
#define CS2_CHK_NUMB 1
#define CS3_EDGE_RD_NUMB 1
#define CS3_EDGE_WR_NUMB 1
#define CS3CS_LVL_NUMB 1
#define CS3_FRQ_NUMB 2
#define CS3_CHK_NUMB 1
// Setup Register 3
//==================
//Reset values
#define CK_FREQ_SET_VAL 0x0
#define CLK_EN_RES_VAL 0x0
//Pos Values
#define CLK_EN_POS 0x0
#define CK_FREQ_POS 0x1
//Width Values
#define CLK_EN_NUMB 1
#define CK_FREQ_NUMB 2
// Setup Register 4
//==================
//Reset values
#define CLK_IN_RES_VAL 0x0
//Pos Values
#define CLK_IN_POS 0x0
//Width Values
#define CLK_IN_NUMB 1
// Setup Register 5
//==================
//Reset values
#define DMA_TX_RES_VAL 0x00
#define IT_RES_VAL 0x00
#define AUTO_TX_RES_VAL 0x00
#define CS_TOGGLE_RES_VAL 0x00
//Pos values
#define DMA_TX_POS 0x00
#define IT_POS 0x01
#define AUTO_TX_POS 0x02
#define CS_TOGGLE_POS 0x03
//Width Values
#define DMA_TX_NUMB 0x01
#define IT_NUMB 0x01
#define AUTO_TX_NUMB 0x01
#define CS_TOGGLE_NUMB 0x01
#define UWIRE_TEST_FIELD_RESET_VALUE(RegisterName,GroupBitName)\
RES_Set(GetGroupBits16(REG32(RegisterName),\
(GroupBitName ## _POS),\
(GroupBitName ## _NUMB))\
==(GroupBitName ## _RES_VAL) ? TEST_OK : \
GroupBitName ## _BAD_RESET_VALUE)
#define UWIRE_TEST_REGISTER_RESET_VALUE(RegisterName)\
RES_Set(REG32(RegisterName)\
==(RegisterName ## _RES_VAL) ? TEST_OK : \
RegisterName ## _BAD_RESET_VALUE)
//===========
// EEPROM
//===========
#define UWIRE_EEPROM_WEN 0x9800 // EEPROM write enable 10011xx...xx
#define UWIRE_EEPROM_ERAL 0x9000 // EEPROM erase all 10010xx...xx
#define UWIRE_EEPROM_WRITE 0xa000 // EEPROM write 101xxxx...xx
#define UWIRE_EEPROM_READ 0xc000 // EEPROM read 110xxxx...xx
#define UWIRE_XL66_CMD_LEN 11 // XL66 EEPROM command length to write
// 3 bits for the command
// 8 bits for the adress
#define UWIRE_M46_CMD_LEN 9 // M46 EEPROM command length to write
#define UWIRE_XL66_SHIFT 5 // XL66 address shift
#define UWIRE_M46_SHIFT 7 // M46 address shift
#define UWIRE_EEPROM_DATA_LEN 16 // EEPROM data length to write
#define UWIRE_XL66_SIZE 5 // XL93LC66 size 128*16
#define UWIRE_M46_SIZE 64 // M93LC46 size 64*16
#define UWIRE_INIT_VALUE 0x5a00 // EEPROM INIT VALUE
// Microchip 93LC46B (no ORG, 16-bit)
#define UWIRE_93LC46B_CMD_LEN 9
#define UWIRE_93LC46B_SHIFT 5
/* void BUSC_WaitStateInit(UWORD32, UWORD32, UWORD32); */
//-----------------------------------------------------------------------
//NAME : UWIRE_Load_TX_Register -
//DESCRIPTION : Load TX register -
//PARAMETERS : -
// data = Data to transmit -
//RETURN VALUE: None -
//-----------------------------------------------------------------------
#define UWIRE_Load_TX_Register(data)\
UWIRE_TDR_REG = (data)
//-----------------------------------------------------------------------
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