📄 uwire.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :uwire.h
//
// Date of Module Modification:6/13/02
// Date of Generation :8/29/02
//
//
//========================================================================
#include "mapping.h"
#include "global_types.h"
#ifndef _UWIRE__H
#define _UWIRE__H
//BEGIN INC GENERATION
//--------------------------------------
//Register Offset
//-------------------
#define UWIRE_RDR_OFFSET 0x00
#define UWIRE_TDR_OFFSET 0x00
#define UWIRE_CSR_OFFSET 0x02
#define UWIRE_SR1_OFFSET 0x04
#define UWIRE_SR2_OFFSET 0x06
#define UWIRE_SR3_OFFSET 0x08
#define UWIRE_SR4_OFFSET 0x0A
#define UWIRE_SR5_OFFSET 0x0C
//UWIRE_RDR
//-------------------
#define UWIRE_RDR REG16(UWIRE_BASE_ADDR_ARM+UWIRE_RDR_OFFSET)
#define UWIRE_RDR_RD_POS 0
#define UWIRE_RDR_RD_NUMB 16
#define UWIRE_RDR_RD_RES_VAL 0xX (undefined)
//R
//UWIRE_TDR
//-------------------
#define UWIRE_TDR REG16(UWIRE_BASE_ADDR_ARM+UWIRE_TDR_OFFSET)
#define UWIRE_TDR_TD_POS 0
#define UWIRE_TDR_TD_NUMB 16
#define UWIRE_TDR_TD_RES_VAL 0xX (undefined)
//W
//UWIRE_CSR
//-------------------
#define UWIRE_CSR REG16(UWIRE_BASE_ADDR_ARM+UWIRE_CSR_OFFSET)
#define UWIRE_CSR_RDRB_POS 15
#define UWIRE_CSR_RDRB_NUMB 1
#define UWIRE_CSR_RDRB_RES_VAL 0x0
//R
#define UWIRE_CSR_CSRB_POS 14
#define UWIRE_CSR_CSRB_NUMB 1
#define UWIRE_CSR_CSRB_RES_VAL 0x0
//R
#define UWIRE_CSR_START_POS 13
#define UWIRE_CSR_START_NUMB 1
#define UWIRE_CSR_START_RES_VAL 0x0
//R/W
#define UWIRE_CSR_CS_CMD_POS 12
#define UWIRE_CSR_CS_CMD_NUMB 1
#define UWIRE_CSR_CS_CMD_RES_VAL 0x0
//R/W
#define UWIRE_CSR_INDEX_POS 10
#define UWIRE_CSR_INDEX_NUMB 2
#define UWIRE_CSR_INDEX_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_CSR_NB_BITS_WR_POS 5
#define UWIRE_CSR_NB_BITS_WR_NUMB 5
#define UWIRE_CSR_NB_BITS_WR_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_CSR_NB_BITS_RD_POS 0
#define UWIRE_CSR_NB_BITS_RD_NUMB 5
#define UWIRE_CSR_NB_BITS_RD_RES_VAL 0xX (undefined)
//R/W
//UWIRE_SR1
//-------------------
#define UWIRE_SR1 REG16(UWIRE_BASE_ADDR_ARM+UWIRE_SR1_OFFSET)
#define UWIRE_SR1_CS1_CHK_POS 11
#define UWIRE_SR1_CS1_CHK_NUMB 1
#define UWIRE_SR1_CS1_CHK_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR1_CS1_FRQ_POS 9
#define UWIRE_SR1_CS1_FRQ_NUMB 2
#define UWIRE_SR1_CS1_FRQ_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR1_CS1CS_LVL_POS 8
#define UWIRE_SR1_CS1CS_LVL_NUMB 1
#define UWIRE_SR1_CS1CS_LVL_RES_VAL 0x0
//R/W
#define UWIRE_SR1_CS1_EDGE_WR_POS 7
#define UWIRE_SR1_CS1_EDGE_WR_NUMB 1
#define UWIRE_SR1_CS1_EDGE_WR_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR1_CS1_EDGE_RD_POS 6
#define UWIRE_SR1_CS1_EDGE_RD_NUMB 1
#define UWIRE_SR1_CS1_EDGE_RD_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR1_CS0_CHK_POS 5
#define UWIRE_SR1_CS0_CHK_NUMB 1
#define UWIRE_SR1_CS0_CHK_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR1_CS0_FRQ_POS 3
#define UWIRE_SR1_CS0_FRQ_NUMB 2
#define UWIRE_SR1_CS0_FRQ_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR1_CS0CS_LVL_POS 2
#define UWIRE_SR1_CS0CS_LVL_NUMB 1
#define UWIRE_SR1_CS0CS_LVL_RES_VAL 0x0
//R/W
#define UWIRE_SR1_CS0_EDGE_WR_POS 1
#define UWIRE_SR1_CS0_EDGE_WR_NUMB 1
#define UWIRE_SR1_CS0_EDGE_WR_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR1_CS0_EDGE_RD_POS 0
#define UWIRE_SR1_CS0_EDGE_RD_NUMB 1
#define UWIRE_SR1_CS0_EDGE_RD_RES_VAL 0xX (undefined)
//R/W
//UWIRE_SR2
//-------------------
#define UWIRE_SR2 REG16(UWIRE_BASE_ADDR_ARM+UWIRE_SR2_OFFSET)
#define UWIRE_SR2_CS3_CHK_POS 11
#define UWIRE_SR2_CS3_CHK_NUMB 1
#define UWIRE_SR2_CS3_CHK_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR2_CS3_FRQ_POS 9
#define UWIRE_SR2_CS3_FRQ_NUMB 2
#define UWIRE_SR2_CS3_FRQ_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR2_CS3CS_LVL_POS 8
#define UWIRE_SR2_CS3CS_LVL_NUMB 1
#define UWIRE_SR2_CS3CS_LVL_RES_VAL 0x0
//R/W
#define UWIRE_SR2_CS3_EDGE_WR_POS 7
#define UWIRE_SR2_CS3_EDGE_WR_NUMB 1
#define UWIRE_SR2_CS3_EDGE_WR_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR2_CS3_EDGE_RD_POS 6
#define UWIRE_SR2_CS3_EDGE_RD_NUMB 1
#define UWIRE_SR2_CS3_EDGE_RD_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR2_CS2_CHK_POS 5
#define UWIRE_SR2_CS2_CHK_NUMB 1
#define UWIRE_SR2_CS2_CHK_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR2_CS2_FRQ_POS 3
#define UWIRE_SR2_CS2_FRQ_NUMB 2
#define UWIRE_SR2_CS2_FRQ_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR2_CS2CS_LVL_POS 2
#define UWIRE_SR2_CS2CS_LVL_NUMB 1
#define UWIRE_SR2_CS2CS_LVL_RES_VAL 0x0
//R/W
#define UWIRE_SR2_CS2_EDGE_WR_POS 1
#define UWIRE_SR2_CS2_EDGE_WR_NUMB 1
#define UWIRE_SR2_CS2_EDGE_WR_RES_VAL 0xX (undefined)
//R/W
#define UWIRE_SR2_CS2_EDGE_RD_POS 0
#define UWIRE_SR2_CS2_EDGE_RD_NUMB 1
#define UWIRE_SR2_CS2_EDGE_RD_RES_VAL 0xX (undefined)
//R/W
//UWIRE_SR3
//-------------------
#define UWIRE_SR3 REG16(UWIRE_BASE_ADDR_ARM+UWIRE_SR3_OFFSET)
#define UWIRE_SR3_CK_FREQ_POS 1
#define UWIRE_SR3_CK_FREQ_NUMB 3
#define UWIRE_SR3_CK_FREQ_RES_VAL 0x000
//R/W
#define UWIRE_SR3_CLK_EN_POS 0
#define UWIRE_SR3_CLK_EN_NUMB 1
#define UWIRE_SR3_CLK_EN_RES_VAL 0x0
//R/W
//UWIRE_SR4
//-------------------
#define UWIRE_SR4 REG16(UWIRE_BASE_ADDR_ARM+UWIRE_SR4_OFFSET)
#define UWIRE_SR4_CLK_IN_POS 0
#define UWIRE_SR4_CLK_IN_NUMB 1
#define UWIRE_SR4_CLK_IN_RES_VAL 0x0
//R/W
//UWIRE_SR5
//-------------------
#define UWIRE_SR5 REG16(UWIRE_BASE_ADDR_ARM+UWIRE_SR5_OFFSET)
#define UWIRE_SR5_AUTO_RX_EN_POS 4
#define UWIRE_SR5_AUTO_RX_EN_NUMB 1
#define UWIRE_SR5_AUTO_RX_EN_RES_VAL 0x0
//R/W
#define UWIRE_SR5_CS_TOGGLE_TX_EN_POS 3
#define UWIRE_SR5_CS_TOGGLE_TX_EN_NUMB 1
#define UWIRE_SR5_CS_TOGGLE_TX_EN_RES_VAL 0x0
//R/W
#define UWIRE_SR5_AUTO_TX_EN_POS 2
#define UWIRE_SR5_AUTO_TX_EN_NUMB 1
#define UWIRE_SR5_AUTO_TX_EN_RES_VAL 0x0
//R/W
#define UWIRE_SR5_IT_EN_POS 1
#define UWIRE_SR5_IT_EN_NUMB 1
#define UWIRE_SR5_IT_EN_RES_VAL 0x0
//R/W
#define UWIRE_SR5_DMA_TX_EN_POS 0
#define UWIRE_SR5_DMA_TX_EN_NUMB 1
#define UWIRE_SR5_DMA_TX_EN_RES_VAL 0x0
//R/W
//--------------------------------------------------
// OFFSET OF REGISTERS IN WORD 16 BITS -
//--------------------------------------------------
//#define UWIRE_CSR_OFFSET SET32BITS(0x1)
//#define UWIRE_SR1_OFFSET SET32BITS(0x2)
//#define UWIRE_SR2_OFFSET SET32BITS(0x3)
//#define UWIRE_SR3_OFFSET SET32BITS(0x4)
//#define UWIRE_SR4_OFFSET SET32BITS(0x5)
//#define UWIRE_SR5_OFFSET SET32BITS(0x6)
//----------------------------------------------------------------------
// ABSOLUTE ADDRESS OF REGISTERs -
//----------------------------------------------------------------------
// transmit and receive register are on the same address
#define UWIRE_TDR_REG (*(REGISTER_UWORD16*) (MAP_UWIRE_REG))
#define UWIRE_RDR_REG (*(REGISTER_UWORD16*) (MAP_UWIRE_REG))
// control & status reg
#define UWIRE_CSR_REG (*(REGISTER_UWORD16*) (MAP_UWIRE_REG + UWIRE_CSR_OFFSET))
// setup register 1
#define UWIRE_SR1_REG (*(REGISTER_UWORD16*) (MAP_UWIRE_REG + UWIRE_SR1_OFFSET))
// setup register 2
#define UWIRE_SR2_REG (*(REGISTER_UWORD16*) (MAP_UWIRE_REG + UWIRE_SR2_OFFSET))
// setup register 3
#define UWIRE_SR3_REG (*(REGISTER_UWORD16*) (MAP_UWIRE_REG + UWIRE_SR3_OFFSET))
// setup register 4
#define UWIRE_SR4_REG (*(REGISTER_UWORD16*) (MAP_UWIRE_REG + UWIRE_SR4_OFFSET))
// setup register 5
#define UWIRE_SR5_REG (*(REGISTER_UWORD16*) (MAP_UWIRE_REG + UWIRE_SR5_OFFSET))
//--------------------------------------------------
// REGISTERS MASK -
//--------------------------------------------------
#define UWIRE_CSR_REG_RESET_VALUE 0x0000
#define UWIRE_SR1_REG_RESET_VALUE 0x0000
#define UWIRE_SR2_REG_RESET_VALUE 0x0000
#define UWIRE_SR3_REG_RESET_VALUE 0x0000
#define UWIRE_SR4_REG_RESET_VALUE 0x0000
#define UWIRE_SR5_REG_RESET_VALUE 0x0000
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