📄 mmc_sdio2.h
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#define MMC_SDIO2_CMD_16_2_TYPE_POS 12
#define MMC_SDIO2_CMD_16_2_TYPE_NUMB 2
#define MMC_SDIO2_CMD_16_2_TYPE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_2_BUSY_POS 11
#define MMC_SDIO2_CMD_16_2_BUSY_NUMB 1
#define MMC_SDIO2_CMD_16_2_BUSY_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_2_RSP_POS 8
#define MMC_SDIO2_CMD_16_2_RSP_NUMB 3
#define MMC_SDIO2_CMD_16_2_RSP_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_2_INAB_POS 7
#define MMC_SDIO2_CMD_16_2_INAB_NUMB 1
#define MMC_SDIO2_CMD_16_2_INAB_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_2_ODTO_POS 6
#define MMC_SDIO2_CMD_16_2_ODTO_NUMB 1
#define MMC_SDIO2_CMD_16_2_ODTO_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_2_INDX_POS 0
#define MMC_SDIO2_CMD_16_2_INDX_NUMB 6
#define MMC_SDIO2_CMD_16_2_INDX_RES_VAL 0x0
//R/W
//-------------------
#define MMC_SDIO2_ARGL_8_0 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGL_OFFSET+0)
#define MMC_SDIO2_ARGL_8_0_ARGL_POS 0
#define MMC_SDIO2_ARGL_8_0_ARGL_NUMB 16
#define MMC_SDIO2_ARGL_8_0_ARGL_RES_VAL 0x0
//R/W
#define MMC_SDIO2_ARGL_8_1 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGL_OFFSET+1)
#define MMC_SDIO2_ARGL_8_1_ARGL_POS 0
#define MMC_SDIO2_ARGL_8_1_ARGL_NUMB 16
#define MMC_SDIO2_ARGL_8_1_ARGL_RES_VAL 0x0
//R/W
#define MMC_SDIO2_ARGL_8_2 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGL_OFFSET+2)
#define MMC_SDIO2_ARGL_8_2_ARGL_POS 0
#define MMC_SDIO2_ARGL_8_2_ARGL_NUMB 16
#define MMC_SDIO2_ARGL_8_2_ARGL_RES_VAL 0x0
//R/W
#define MMC_SDIO2_ARGL_8_3 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGL_OFFSET+3)
#define MMC_SDIO2_ARGL_8_3_ARGL_POS 0
#define MMC_SDIO2_ARGL_8_3_ARGL_NUMB 16
#define MMC_SDIO2_ARGL_8_3_ARGL_RES_VAL 0x0
//R/W
#define MMC_SDIO2_ARGL_16_0 REG16(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGL_OFFSET+0)
#define MMC_SDIO2_ARGL_16_0_ARGL_POS 0
#define MMC_SDIO2_ARGL_16_0_ARGL_NUMB 16
#define MMC_SDIO2_ARGL_16_0_ARGL_RES_VAL 0x0
//R/W
#define MMC_SDIO2_ARGL_16_2 REG16(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGL_OFFSET+2)
#define MMC_SDIO2_ARGL_16_2_ARGL_POS 0
#define MMC_SDIO2_ARGL_16_2_ARGL_NUMB 16
#define MMC_SDIO2_ARGL_16_2_ARGL_RES_VAL 0x0
//R/W
//-------------------
#define MMC_SDIO2_ARGH_8_0 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGH_OFFSET+0)
#define MMC_SDIO2_ARGH_8_0_ARGH_POS 0
#define MMC_SDIO2_ARGH_8_0_ARGH_NUMB 16
#define MMC_SDIO2_ARGH_8_0_ARGH_RES_VAL 0x0
//R/W
#define MMC_SDIO2_ARGH_8_1 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGH_OFFSET+1)
#define MMC_SDIO2_ARGH_8_1_ARGH_POS 0
#define MMC_SDIO2_ARGH_8_1_ARGH_NUMB 16
#define MMC_SDIO2_ARGH_8_1_ARGH_RES_VAL 0x0
//R/W
#define MMC_SDIO2_ARGH_8_2 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGH_OFFSET+2)
#define MMC_SDIO2_ARGH_8_2_ARGH_POS 0
#define MMC_SDIO2_ARGH_8_2_ARGH_NUMB 16
#define MMC_SDIO2_ARGH_8_2_ARGH_RES_VAL 0x0
//R/W
#define MMC_SDIO2_ARGH_8_3 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGH_OFFSET+3)
#define MMC_SDIO2_ARGH_8_3_ARGH_POS 0
#define MMC_SDIO2_ARGH_8_3_ARGH_NUMB 16
#define MMC_SDIO2_ARGH_8_3_ARGH_RES_VAL 0x0
//R/W
#define MMC_SDIO2_ARGH_16_0 REG16(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGH_OFFSET+0)
#define MMC_SDIO2_ARGH_16_0_ARGH_POS 0
#define MMC_SDIO2_ARGH_16_0_ARGH_NUMB 16
#define MMC_SDIO2_ARGH_16_0_ARGH_RES_VAL 0x0
//R/W
#define MMC_SDIO2_ARGH_16_2 REG16(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_ARGH_OFFSET+2)
#define MMC_SDIO2_ARGH_16_2_ARGH_POS 0
#define MMC_SDIO2_ARGH_16_2_ARGH_NUMB 16
#define MMC_SDIO2_ARGH_16_2_ARGH_RES_VAL 0x0
//R/W
//-------------------
#define MMC_SDIO2_CON_8_0 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CON_OFFSET+0)
#define MMC_SDIO2_CON_8_0_DW_POS 15
#define MMC_SDIO2_CON_8_0_DW_NUMB 1
#define MMC_SDIO2_CON_8_0_DW_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_0_RESERVED_POS 14
#define MMC_SDIO2_CON_8_0_RESERVED_NUMB 1
#define MMC_SDIO2_CON_8_0_RESERVED_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_0_MODE_POS 12
#define MMC_SDIO2_CON_8_0_MODE_NUMB 2
#define MMC_SDIO2_CON_8_0_MODE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_0_POW_POS 11
#define MMC_SDIO2_CON_8_0_POW_NUMB 1
#define MMC_SDIO2_CON_8_0_POW_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_0_BE_POS 10
#define MMC_SDIO2_CON_8_0_BE_NUMB 1
#define MMC_SDIO2_CON_8_0_BE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_0_CLKD_POS 0
#define MMC_SDIO2_CON_8_0_CLKD_NUMB 10
#define MMC_SDIO2_CON_8_0_CLKD_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_1 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CON_OFFSET+1)
#define MMC_SDIO2_CON_8_1_DW_POS 15
#define MMC_SDIO2_CON_8_1_DW_NUMB 1
#define MMC_SDIO2_CON_8_1_DW_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_1_RESERVED_POS 14
#define MMC_SDIO2_CON_8_1_RESERVED_NUMB 1
#define MMC_SDIO2_CON_8_1_RESERVED_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_1_MODE_POS 12
#define MMC_SDIO2_CON_8_1_MODE_NUMB 2
#define MMC_SDIO2_CON_8_1_MODE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_1_POW_POS 11
#define MMC_SDIO2_CON_8_1_POW_NUMB 1
#define MMC_SDIO2_CON_8_1_POW_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_1_BE_POS 10
#define MMC_SDIO2_CON_8_1_BE_NUMB 1
#define MMC_SDIO2_CON_8_1_BE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_1_CLKD_POS 0
#define MMC_SDIO2_CON_8_1_CLKD_NUMB 10
#define MMC_SDIO2_CON_8_1_CLKD_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_2 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CON_OFFSET+2)
#define MMC_SDIO2_CON_8_2_DW_POS 15
#define MMC_SDIO2_CON_8_2_DW_NUMB 1
#define MMC_SDIO2_CON_8_2_DW_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_2_RESERVED_POS 14
#define MMC_SDIO2_CON_8_2_RESERVED_NUMB 1
#define MMC_SDIO2_CON_8_2_RESERVED_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_2_MODE_POS 12
#define MMC_SDIO2_CON_8_2_MODE_NUMB 2
#define MMC_SDIO2_CON_8_2_MODE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_2_POW_POS 11
#define MMC_SDIO2_CON_8_2_POW_NUMB 1
#define MMC_SDIO2_CON_8_2_POW_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_2_BE_POS 10
#define MMC_SDIO2_CON_8_2_BE_NUMB 1
#define MMC_SDIO2_CON_8_2_BE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_2_CLKD_POS 0
#define MMC_SDIO2_CON_8_2_CLKD_NUMB 10
#define MMC_SDIO2_CON_8_2_CLKD_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_3 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CON_OFFSET+3)
#define MMC_SDIO2_CON_8_3_DW_POS 15
#define MMC_SDIO2_CON_8_3_DW_NUMB 1
#define MMC_SDIO2_CON_8_3_DW_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_3_RESERVED_POS 14
#define MMC_SDIO2_CON_8_3_RESERVED_NUMB 1
#define MMC_SDIO2_CON_8_3_RESERVED_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_3_MODE_POS 12
#define MMC_SDIO2_CON_8_3_MODE_NUMB 2
#define MMC_SDIO2_CON_8_3_MODE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_3_POW_POS 11
#define MMC_SDIO2_CON_8_3_POW_NUMB 1
#define MMC_SDIO2_CON_8_3_POW_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_3_BE_POS 10
#define MMC_SDIO2_CON_8_3_BE_NUMB 1
#define MMC_SDIO2_CON_8_3_BE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_8_3_CLKD_POS 0
#define MMC_SDIO2_CON_8_3_CLKD_NUMB 10
#define MMC_SDIO2_CON_8_3_CLKD_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_16_0 REG16(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CON_OFFSET+0)
#define MMC_SDIO2_CON_16_0_DW_POS 15
#define MMC_SDIO2_CON_16_0_DW_NUMB 1
#define MMC_SDIO2_CON_16_0_DW_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_16_0_RESERVED_POS 14
#define MMC_SDIO2_CON_16_0_RESERVED_NUMB 1
#define MMC_SDIO2_CON_16_0_RESERVED_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_16_0_MODE_POS 12
#define MMC_SDIO2_CON_16_0_MODE_NUMB 2
#define MMC_SDIO2_CON_16_0_MODE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CON_16_0_POW_POS 11
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