📄 mmc_sdio2.h
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/*Header modified by DSP-CONVERT V1.01 Script on Wed Aug 28 12:10:52 MEST 2002*/
//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :mmc_sdio2.h
//
// Date of Module Modification:8/21/02
// Date of Generation :8/21/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _MMC_SDIO2__H
#define _MMC_SDIO2__H
//BEGIN INC GENERATION
//--------------------------------------
#define MMC_SDIO2_CMD_OFFSET (0x00)
#define MMC_SDIO2_ARGL_OFFSET (0x04)
#define MMC_SDIO2_ARGH_OFFSET (0x08)
#define MMC_SDIO2_CON_OFFSET (0x0C)
#define MMC_SDIO2_STAT_OFFSET (0x10)
#define MMC_SDIO2_IE_OFFSET (0x14)
#define MMC_SDIO2_CTO_OFFSET (0x18)
#define MMC_SDIO2_DTO_OFFSET (0x1C)
#define MMC_SDIO2_DATA_OFFSET (0x20)
#define MMC_SDIO2_BLEN_OFFSET (0x24)
#define MMC_SDIO2_NBLK_OFFSET (0x28)
#define MMC_SDIO2_BUF_OFFSET (0x2C)
#define MMC_SDIO2_SPI_OFFSET (0x30)
#define MMC_SDIO2_SDIO_OFFSET (0x34)
#define MMC_SDIO2_SYST_OFFSET (0x38)
#define MMC_SDIO2_REV_OFFSET (0x3C)
#define MMC_SDIO2_RSP0_OFFSET (0x40)
#define MMC_SDIO2_RSP1_OFFSET (0x44)
#define MMC_SDIO2_RSP2_OFFSET (0x48)
#define MMC_SDIO2_RSP3_OFFSET (0x4C)
#define MMC_SDIO2_RSP4_OFFSET (0x50)
#define MMC_SDIO2_RSP5_OFFSET (0x54)
#define MMC_SDIO2_RSP6_OFFSET (0x58)
#define MMC_SDIO2_RSP7_OFFSET (0x5C)
#define MMC_SDIO2_IOSR_OFFSET (0x60)
#define MMC_SDIO2_SYSC_OFFSET (0x64)
#define MMC_SDIO2_SYSS_OFFSET (0x68)
//MMC_SDIO2_CMD
//-------------------
#define MMC_SDIO2_CMD_8_0 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CMD_OFFSET+0)
#define MMC_SDIO2_CMD_8_0_DDIR_POS 15
#define MMC_SDIO2_CMD_8_0_DDIR_NUMB 1
#define MMC_SDIO2_CMD_8_0_DDIR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_0_SHR_POS 14
#define MMC_SDIO2_CMD_8_0_SHR_NUMB 1
#define MMC_SDIO2_CMD_8_0_SHR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_0_TYPE_POS 12
#define MMC_SDIO2_CMD_8_0_TYPE_NUMB 2
#define MMC_SDIO2_CMD_8_0_TYPE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_0_BUSY_POS 11
#define MMC_SDIO2_CMD_8_0_BUSY_NUMB 1
#define MMC_SDIO2_CMD_8_0_BUSY_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_0_RSP_POS 8
#define MMC_SDIO2_CMD_8_0_RSP_NUMB 3
#define MMC_SDIO2_CMD_8_0_RSP_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_0_INAB_POS 7
#define MMC_SDIO2_CMD_8_0_INAB_NUMB 1
#define MMC_SDIO2_CMD_8_0_INAB_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_0_ODTO_POS 6
#define MMC_SDIO2_CMD_8_0_ODTO_NUMB 1
#define MMC_SDIO2_CMD_8_0_ODTO_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_0_INDX_POS 0
#define MMC_SDIO2_CMD_8_0_INDX_NUMB 6
#define MMC_SDIO2_CMD_8_0_INDX_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_1 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CMD_OFFSET+1)
#define MMC_SDIO2_CMD_8_1_DDIR_POS 15
#define MMC_SDIO2_CMD_8_1_DDIR_NUMB 1
#define MMC_SDIO2_CMD_8_1_DDIR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_1_SHR_POS 14
#define MMC_SDIO2_CMD_8_1_SHR_NUMB 1
#define MMC_SDIO2_CMD_8_1_SHR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_1_TYPE_POS 12
#define MMC_SDIO2_CMD_8_1_TYPE_NUMB 2
#define MMC_SDIO2_CMD_8_1_TYPE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_1_BUSY_POS 11
#define MMC_SDIO2_CMD_8_1_BUSY_NUMB 1
#define MMC_SDIO2_CMD_8_1_BUSY_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_1_RSP_POS 8
#define MMC_SDIO2_CMD_8_1_RSP_NUMB 3
#define MMC_SDIO2_CMD_8_1_RSP_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_1_INAB_POS 7
#define MMC_SDIO2_CMD_8_1_INAB_NUMB 1
#define MMC_SDIO2_CMD_8_1_INAB_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_1_ODTO_POS 6
#define MMC_SDIO2_CMD_8_1_ODTO_NUMB 1
#define MMC_SDIO2_CMD_8_1_ODTO_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_1_INDX_POS 0
#define MMC_SDIO2_CMD_8_1_INDX_NUMB 6
#define MMC_SDIO2_CMD_8_1_INDX_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_2 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CMD_OFFSET+2)
#define MMC_SDIO2_CMD_8_2_DDIR_POS 15
#define MMC_SDIO2_CMD_8_2_DDIR_NUMB 1
#define MMC_SDIO2_CMD_8_2_DDIR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_2_SHR_POS 14
#define MMC_SDIO2_CMD_8_2_SHR_NUMB 1
#define MMC_SDIO2_CMD_8_2_SHR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_2_TYPE_POS 12
#define MMC_SDIO2_CMD_8_2_TYPE_NUMB 2
#define MMC_SDIO2_CMD_8_2_TYPE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_2_BUSY_POS 11
#define MMC_SDIO2_CMD_8_2_BUSY_NUMB 1
#define MMC_SDIO2_CMD_8_2_BUSY_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_2_RSP_POS 8
#define MMC_SDIO2_CMD_8_2_RSP_NUMB 3
#define MMC_SDIO2_CMD_8_2_RSP_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_2_INAB_POS 7
#define MMC_SDIO2_CMD_8_2_INAB_NUMB 1
#define MMC_SDIO2_CMD_8_2_INAB_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_2_ODTO_POS 6
#define MMC_SDIO2_CMD_8_2_ODTO_NUMB 1
#define MMC_SDIO2_CMD_8_2_ODTO_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_2_INDX_POS 0
#define MMC_SDIO2_CMD_8_2_INDX_NUMB 6
#define MMC_SDIO2_CMD_8_2_INDX_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_3 REG8(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CMD_OFFSET+3)
#define MMC_SDIO2_CMD_8_3_DDIR_POS 15
#define MMC_SDIO2_CMD_8_3_DDIR_NUMB 1
#define MMC_SDIO2_CMD_8_3_DDIR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_3_SHR_POS 14
#define MMC_SDIO2_CMD_8_3_SHR_NUMB 1
#define MMC_SDIO2_CMD_8_3_SHR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_3_TYPE_POS 12
#define MMC_SDIO2_CMD_8_3_TYPE_NUMB 2
#define MMC_SDIO2_CMD_8_3_TYPE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_3_BUSY_POS 11
#define MMC_SDIO2_CMD_8_3_BUSY_NUMB 1
#define MMC_SDIO2_CMD_8_3_BUSY_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_3_RSP_POS 8
#define MMC_SDIO2_CMD_8_3_RSP_NUMB 3
#define MMC_SDIO2_CMD_8_3_RSP_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_3_INAB_POS 7
#define MMC_SDIO2_CMD_8_3_INAB_NUMB 1
#define MMC_SDIO2_CMD_8_3_INAB_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_3_ODTO_POS 6
#define MMC_SDIO2_CMD_8_3_ODTO_NUMB 1
#define MMC_SDIO2_CMD_8_3_ODTO_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_8_3_INDX_POS 0
#define MMC_SDIO2_CMD_8_3_INDX_NUMB 6
#define MMC_SDIO2_CMD_8_3_INDX_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_0 REG16(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CMD_OFFSET+0)
#define MMC_SDIO2_CMD_16_0_DDIR_POS 15
#define MMC_SDIO2_CMD_16_0_DDIR_NUMB 1
#define MMC_SDIO2_CMD_16_0_DDIR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_0_SHR_POS 14
#define MMC_SDIO2_CMD_16_0_SHR_NUMB 1
#define MMC_SDIO2_CMD_16_0_SHR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_0_TYPE_POS 12
#define MMC_SDIO2_CMD_16_0_TYPE_NUMB 2
#define MMC_SDIO2_CMD_16_0_TYPE_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_0_BUSY_POS 11
#define MMC_SDIO2_CMD_16_0_BUSY_NUMB 1
#define MMC_SDIO2_CMD_16_0_BUSY_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_0_RSP_POS 8
#define MMC_SDIO2_CMD_16_0_RSP_NUMB 3
#define MMC_SDIO2_CMD_16_0_RSP_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_0_INAB_POS 7
#define MMC_SDIO2_CMD_16_0_INAB_NUMB 1
#define MMC_SDIO2_CMD_16_0_INAB_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_0_ODTO_POS 6
#define MMC_SDIO2_CMD_16_0_ODTO_NUMB 1
#define MMC_SDIO2_CMD_16_0_ODTO_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_0_INDX_POS 0
#define MMC_SDIO2_CMD_16_0_INDX_NUMB 6
#define MMC_SDIO2_CMD_16_0_INDX_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_2 REG16(MMC_SDIO2_BASE_ADDR_ARM+MMC_SDIO2_CMD_OFFSET+2)
#define MMC_SDIO2_CMD_16_2_DDIR_POS 15
#define MMC_SDIO2_CMD_16_2_DDIR_NUMB 1
#define MMC_SDIO2_CMD_16_2_DDIR_RES_VAL 0x0
//R/W
#define MMC_SDIO2_CMD_16_2_SHR_POS 14
#define MMC_SDIO2_CMD_16_2_SHR_NUMB 1
#define MMC_SDIO2_CMD_16_2_SHR_RES_VAL 0x0
//R/W
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