camcaccint.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define EASIL1_CAMCCC_IRQENABLEFIFO_UF_IRQ_ENWrite32                            CAMC_BASE_EASIL1 + 308                                                          
#define EASIL1_CAMCCC_IRQENABLEFIFO_UF_IRQ_ENWritefifo_uf_irq_en_mask32         CAMC_BASE_EASIL1 + 309                                                          
#define EASIL1_CAMCCC_IRQENABLEFIFO_UF_IRQ_ENWritefifo_uf_irq_en_nomask32       CAMC_BASE_EASIL1 + 310                                                          
#define EASIL1_CAMCCC_IRQENABLEFIFO_UF_IRQ_ENSet32                              CAMC_BASE_EASIL1 + 311                                                          
#define EASIL1_CAMCCC_CTRLReadRegister32                                        CAMC_BASE_EASIL1 + 312                                                          
#define EASIL1_CAMCCC_CTRLWriteRegister32                                       CAMC_BASE_EASIL1 + 313                                                          
#define EASIL1_CAMCCC_CTRLCC_RSTRead32                                          CAMC_BASE_EASIL1 + 314                                                          
#define EASIL1_CAMCCC_CTRLCC_RSTGet32                                           CAMC_BASE_EASIL1 + 315                                                          
#define EASIL1_CAMCCC_CTRLCC_RSTWrite32                                         CAMC_BASE_EASIL1 + 316                                                          
#define EASIL1_CAMCCC_CTRLCC_RSTSet32                                           CAMC_BASE_EASIL1 + 317                                                          
#define EASIL1_CAMCCC_CTRLCC_FRAME_TRIGRead32                                   CAMC_BASE_EASIL1 + 318                                                          
#define EASIL1_CAMCCC_CTRLCC_FRAME_TRIGGet32                                    CAMC_BASE_EASIL1 + 319                                                          
#define EASIL1_CAMCCC_CTRLCC_FRAME_TRIGWrite32                                  CAMC_BASE_EASIL1 + 320                                                          
#define EASIL1_CAMCCC_CTRLCC_FRAME_TRIGSet32                                    CAMC_BASE_EASIL1 + 321                                                          
#define EASIL1_CAMCCC_CTRLCC_ENRead32                                           CAMC_BASE_EASIL1 + 322                                                          
#define EASIL1_CAMCCC_CTRLCC_ENGet32                                            CAMC_BASE_EASIL1 + 323                                                          
#define EASIL1_CAMCCC_CTRLCC_ENWrite32                                          CAMC_BASE_EASIL1 + 324                                                          
#define EASIL1_CAMCCC_CTRLCC_ENSet32                                            CAMC_BASE_EASIL1 + 325                                                          
#define EASIL1_CAMCCC_CTRLNoBT_SYNCHRORead32                                    CAMC_BASE_EASIL1 + 326                                                          
#define EASIL1_CAMCCC_CTRLNoBT_SYNCHROReadIsHigh32                              CAMC_BASE_EASIL1 + 327                                                          
#define EASIL1_CAMCCC_CTRLNoBT_SYNCHROReadIsLow2High32                          CAMC_BASE_EASIL1 + 328                                                          
#define EASIL1_CAMCCC_CTRLNoBT_SYNCHROGet32                                     CAMC_BASE_EASIL1 + 329                                                          
#define EASIL1_CAMCCC_CTRLNoBT_SYNCHROIsHigh32                                  CAMC_BASE_EASIL1 + 330                                                          
#define EASIL1_CAMCCC_CTRLNoBT_SYNCHROIsLow2High32                              CAMC_BASE_EASIL1 + 331                                                          
#define EASIL1_CAMCCC_CTRLNoBT_SYNCHROWrite32                                   CAMC_BASE_EASIL1 + 332                                                          
#define EASIL1_CAMCCC_CTRLNoBT_SYNCHROWriteHigh32                               CAMC_BASE_EASIL1 + 333                                                          
#define EASIL1_CAMCCC_CTRLNoBT_SYNCHROWriteLow2High32                           CAMC_BASE_EASIL1 + 334                                                          
#define EASIL1_CAMCCC_CTRLNoBT_SYNCHROSet32                                     CAMC_BASE_EASIL1 + 335                                                          
#define EASIL1_CAMCCC_CTRLBT_CORRECTRead32                                      CAMC_BASE_EASIL1 + 336                                                          
#define EASIL1_CAMCCC_CTRLBT_CORRECTReadIscorr_not_enable32                     CAMC_BASE_EASIL1 + 337                                                          
#define EASIL1_CAMCCC_CTRLBT_CORRECTReadIscorr_enable32                         CAMC_BASE_EASIL1 + 338                                                          
#define EASIL1_CAMCCC_CTRLBT_CORRECTGet32                                       CAMC_BASE_EASIL1 + 339                                                          
#define EASIL1_CAMCCC_CTRLBT_CORRECTIscorr_not_enable32                         CAMC_BASE_EASIL1 + 340                                                          
#define EASIL1_CAMCCC_CTRLBT_CORRECTIscorr_enable32                             CAMC_BASE_EASIL1 + 341                                                          
#define EASIL1_CAMCCC_CTRLBT_CORRECTWrite32                                     CAMC_BASE_EASIL1 + 342                                                          
#define EASIL1_CAMCCC_CTRLBT_CORRECTWritecorr_not_enable32                      CAMC_BASE_EASIL1 + 343                                                          
#define EASIL1_CAMCCC_CTRLBT_CORRECTWritecorr_enable32                          CAMC_BASE_EASIL1 + 344                                                          
#define EASIL1_CAMCCC_CTRLBT_CORRECTSet32                                       CAMC_BASE_EASIL1 + 345                                                          
#define EASIL1_CAMCCC_CTRLPAR_ORDERCAMRead32                                    CAMC_BASE_EASIL1 + 346                                                          
#define EASIL1_CAMCCC_CTRLPAR_ORDERCAMReadIsswap_not_enable32                   CAMC_BASE_EASIL1 + 347                                                          
#define EASIL1_CAMCCC_CTRLPAR_ORDERCAMReadIsswap_enable32                       CAMC_BASE_EASIL1 + 348                                                          
#define EASIL1_CAMCCC_CTRLPAR_ORDERCAMGet32                                     CAMC_BASE_EASIL1 + 349                                                          
#define EASIL1_CAMCCC_CTRLPAR_ORDERCAMIsswap_not_enable32                       CAMC_BASE_EASIL1 + 350                                                          
#define EASIL1_CAMCCC_CTRLPAR_ORDERCAMIsswap_enable32                           CAMC_BASE_EASIL1 + 351                                                          
#define EASIL1_CAMCCC_CTRLPAR_ORDERCAMWrite32                                   CAMC_BASE_EASIL1 + 352                                                          
#define EASIL1_CAMCCC_CTRLPAR_ORDERCAMWriteswap_not_enable32                    CAMC_BASE_EASIL1 + 353                                                          
#define EASIL1_CAMCCC_CTRLPAR_ORDERCAMWriteswap_enable32                        CAMC_BASE_EASIL1 + 354                                                          
#define EASIL1_CAMCCC_CTRLPAR_ORDERCAMSet32                                     CAMC_BASE_EASIL1 + 355                                                          
#define EASIL1_CAMCCC_CTRLPAR_CLK_POLRead32                                     CAMC_BASE_EASIL1 + 356                                                          
#define EASIL1_CAMCCC_CTRLPAR_CLK_POLReadIsclk_not_inverted32                   CAMC_BASE_EASIL1 + 357                                                          
#define EASIL1_CAMCCC_CTRLPAR_CLK_POLReadIsclk_inverted32                       CAMC_BASE_EASIL1 + 358                                                          
#define EASIL1_CAMCCC_CTRLPAR_CLK_POLGet32                                      CAMC_BASE_EASIL1 + 359                                                          
#define EASIL1_CAMCCC_CTRLPAR_CLK_POLIsclk_not_inverted32                       CAMC_BASE_EASIL1 + 360                                                          
#define EASIL1_CAMCCC_CTRLPAR_CLK_POLIsclk_inverted32                           CAMC_BASE_EASIL1 + 361                                                          
#define EASIL1_CAMCCC_CTRLPAR_CLK_POLWrite32                                    CAMC_BASE_EASIL1 + 362                                                          
#define EASIL1_CAMCCC_CTRLPAR_CLK_POLWriteclk_not_inverted32                    CAMC_BASE_EASIL1 + 363                                                          
#define EASIL1_CAMCCC_CTRLPAR_CLK_POLWriteclk_inverted32                        CAMC_BASE_EASIL1 + 364                                                          
#define EASIL1_CAMCCC_CTRLPAR_CLK_POLSet32                                      CAMC_BASE_EASIL1 + 365                                                          
#define EASIL1_CAMCCC_CTRLNOBT_HS_POLRead32                                     CAMC_BASE_EASIL1 + 366                                                          
#define EASIL1_CAMCCC_CTRLNOBT_HS_POLReadIsCAM_P_HS_active_high32               CAMC_BASE_EASIL1 + 367                                                          
#define EASIL1_CAMCCC_CTRLNOBT_HS_POLReadIsCAM_P_HS_active_low32                CAMC_BASE_EASIL1 + 368                                                          
#define EASIL1_CAMCCC_CTRLNOBT_HS_POLGet32                                      CAMC_BASE_EASIL1 + 369                                                          
#define EASIL1_CAMCCC_CTRLNOBT_HS_POLIsCAM_P_HS_active_high32                   CAMC_BASE_EASIL1 + 370                                                          
#define EASIL1_CAMCCC_CTRLNOBT_HS_POLIsCAM_P_HS_active_low32                    CAMC_BASE_EASIL1 + 371                                                          
#define EASIL1_CAMCCC_CTRLNOBT_HS_POLWrite32                                    CAMC_BASE_EASIL1 + 372                                                          
#define EASIL1_CAMCCC_CTRLNOBT_HS_POLWriteCAM_P_HS_active_high32                CAMC_BASE_EASIL1 + 373                                                          
#define EASIL1_CAMCCC_CTRLNOBT_HS_POLWriteCAM_P_HS_active_low32                 CAMC_BASE_EASIL1 + 374                                                          
#define EASIL1_CAMCCC_CTRLNOBT_HS_POLSet32                                      CAMC_BASE_EASIL1 + 375                                                          
#define EASIL1_CAMCCC_CTRLNOBT_VS_POLRead32                                     CAMC_BASE_EASIL1 + 376                                                          
#define EASIL1_CAMCCC_CTRLNOBT_VS_POLReadIsCAM_P_VS_active_high32               CAMC_BASE_EASIL1 + 377                                                          
#define EASIL1_CAMCCC_CTRLNOBT_VS_POLReadIsCAM_P_VS_active_low32                CAMC_BASE_EASIL1 + 378                                                          
#define EASIL1_CAMCCC_CTRLNOBT_VS_POLGet32                                      CAMC_BASE_EASIL1 + 379                                                          
#define EASIL1_CAMCCC_CTRLNOBT_VS_POLIsCAM_P_VS_active_high32                   CAMC_BASE_EASIL1 + 380                                                          
#define EASIL1_CAMCCC_CTRLNOBT_VS_POLIsCAM_P_VS_active_low32                    CAMC_BASE_EASIL1 + 381                                                          
#define EASIL1_CAMCCC_CTRLNOBT_VS_POLWrite32                                    CAMC_BASE_EASIL1 + 382                                                          
#define EASIL1_CAMCCC_CTRLNOBT_VS_POLWriteCAM_P_VS_active_high32                CAMC_BASE_EASIL1 + 383                                                          
#define EASIL1_CAMCCC_CTRLNOBT_VS_POLWriteCAM_P_VS_active_low32                 CAMC_BASE_EASIL1 + 384                                                          
#define EASIL1_CAMCCC_CTRLNOBT_VS_POLSet32                                      CAMC_BASE_EASIL1 + 385                                                          
#define EASIL1_CAMCCC_CTRLPAR_MODERead32                                        CAMC_BASE_EASIL1 + 386                                                          
#define EASIL1_CAMCCC_CTRLPAR_MODEReadIsparr_NOBT_8bit32                        CAMC_BASE_EASIL1 + 387                                                          
#define EASIL1_CAMCCC_CTRLPAR_MODEReadIsparr_NOBT_10bit32                       CAMC_BASE_EASIL1 + 388                                                          
#define EASIL1_CAMCCC_CTRLPAR_MODEReadIsparr_NOBT_12bit32                       CAMC_BASE_EASIL1 + 389                                                          
#define EASIL1_CAMCCC_CTRLPAR_MODEReadIsreserved132                             CAMC_BASE_EASIL1 + 390                                                          
#define EASIL1_CAMCCC_CTRLPAR_MODEReadIsparr_BT_8bit32                          CAMC_BASE_EASIL1 + 391                                                          
#define EASIL1_CAMCCC_CTRLPAR_MODEReadIsparr_BT_10bit32                         CAMC_BASE_EASIL1 + 392                                                          
#define EASIL1_CAMCCC_CTRLPAR_MODEReadIsreserved232                             CAMC_BASE_EASIL1 + 393