camcaccint.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define EASIL1_CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQRead32                           CAMC_BASE_EASIL1 + 130                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQReadIsfase_r32                   CAMC_BASE_EASIL1 + 131                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQReadIstrue_r32                   CAMC_BASE_EASIL1 + 132                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQGet32                            CAMC_BASE_EASIL1 + 133                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQIsfase_r32                       CAMC_BASE_EASIL1 + 134                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQIstrue_r32                       CAMC_BASE_EASIL1 + 135                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQWrite32                          CAMC_BASE_EASIL1 + 136                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQWritestatUc_w32                  CAMC_BASE_EASIL1 + 137                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQWritestatrst_w32                 CAMC_BASE_EASIL1 + 138                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_NOEMPTY_IRQSet32                            CAMC_BASE_EASIL1 + 139                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_FULL_IRQRead32                              CAMC_BASE_EASIL1 + 140                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_FULL_IRQReadIsfase_r32                      CAMC_BASE_EASIL1 + 141                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_FULL_IRQReadIstrue_r32                      CAMC_BASE_EASIL1 + 142                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_FULL_IRQGet32                               CAMC_BASE_EASIL1 + 143                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_FULL_IRQIsfase_r32                          CAMC_BASE_EASIL1 + 144                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_FULL_IRQIstrue_r32                          CAMC_BASE_EASIL1 + 145                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_FULL_IRQWrite32                             CAMC_BASE_EASIL1 + 146                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_FULL_IRQWritestatUc_w32                     CAMC_BASE_EASIL1 + 147                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_FULL_IRQWritestatrst_w32                    CAMC_BASE_EASIL1 + 148                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_FULL_IRQSet32                               CAMC_BASE_EASIL1 + 149                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_THR_IRQRead32                               CAMC_BASE_EASIL1 + 150                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_THR_IRQReadIsfase_r32                       CAMC_BASE_EASIL1 + 151                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_THR_IRQReadIstrue_r32                       CAMC_BASE_EASIL1 + 152                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_THR_IRQGet32                                CAMC_BASE_EASIL1 + 153                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_THR_IRQIsfase_r32                           CAMC_BASE_EASIL1 + 154                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_THR_IRQIstrue_r32                           CAMC_BASE_EASIL1 + 155                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_THR_IRQWrite32                              CAMC_BASE_EASIL1 + 156                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_THR_IRQWritestatUc_w32                      CAMC_BASE_EASIL1 + 157                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_THR_IRQWritestatrst_w32                     CAMC_BASE_EASIL1 + 158                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_THR_IRQSet32                                CAMC_BASE_EASIL1 + 159                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_OF_IRQRead32                                CAMC_BASE_EASIL1 + 160                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_OF_IRQReadIsfase_r32                        CAMC_BASE_EASIL1 + 161                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_OF_IRQReadIstrue_r32                        CAMC_BASE_EASIL1 + 162                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_OF_IRQGet32                                 CAMC_BASE_EASIL1 + 163                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_OF_IRQIsfase_r32                            CAMC_BASE_EASIL1 + 164                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_OF_IRQIstrue_r32                            CAMC_BASE_EASIL1 + 165                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_OF_IRQWrite32                               CAMC_BASE_EASIL1 + 166                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_OF_IRQWritestatUc_w32                       CAMC_BASE_EASIL1 + 167                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_OF_IRQWritestatrst_w32                      CAMC_BASE_EASIL1 + 168                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_OF_IRQSet32                                 CAMC_BASE_EASIL1 + 169                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_UF_IRQRead32                                CAMC_BASE_EASIL1 + 170                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_UF_IRQReadIsfase_r32                        CAMC_BASE_EASIL1 + 171                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_UF_IRQReadIstrue_r32                        CAMC_BASE_EASIL1 + 172                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_UF_IRQGet32                                 CAMC_BASE_EASIL1 + 173                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_UF_IRQIsfase_r32                            CAMC_BASE_EASIL1 + 174                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_UF_IRQIstrue_r32                            CAMC_BASE_EASIL1 + 175                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_UF_IRQWrite32                               CAMC_BASE_EASIL1 + 176                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_UF_IRQWritestatUc_w32                       CAMC_BASE_EASIL1 + 177                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_UF_IRQWritestatrst_w32                      CAMC_BASE_EASIL1 + 178                                                          
#define EASIL1_CAMCCC_IRQSTATUSFIFO_UF_IRQSet32                                 CAMC_BASE_EASIL1 + 179                                                          
#define EASIL1_CAMCCC_IRQENABLEReadRegister32                                   CAMC_BASE_EASIL1 + 180                                                          
#define EASIL1_CAMCCC_IRQENABLEWriteRegister32                                  CAMC_BASE_EASIL1 + 181                                                          
#define EASIL1_CAMCCC_IRQENABLEFS_IRQ_ENRead32                                  CAMC_BASE_EASIL1 + 182                                                          
#define EASIL1_CAMCCC_IRQENABLEFS_IRQ_ENReadIsfs_irq_en_mask32                  CAMC_BASE_EASIL1 + 183                                                          
#define EASIL1_CAMCCC_IRQENABLEFS_IRQ_ENReadIsfs_irq_en_nomask32                CAMC_BASE_EASIL1 + 184                                                          
#define EASIL1_CAMCCC_IRQENABLEFS_IRQ_ENGet32                                   CAMC_BASE_EASIL1 + 185                                                          
#define EASIL1_CAMCCC_IRQENABLEFS_IRQ_ENIsfs_irq_en_mask32                      CAMC_BASE_EASIL1 + 186                                                          
#define EASIL1_CAMCCC_IRQENABLEFS_IRQ_ENIsfs_irq_en_nomask32                    CAMC_BASE_EASIL1 + 187                                                          
#define EASIL1_CAMCCC_IRQENABLEFS_IRQ_ENWrite32                                 CAMC_BASE_EASIL1 + 188                                                          
#define EASIL1_CAMCCC_IRQENABLEFS_IRQ_ENWritefs_irq_en_mask32                   CAMC_BASE_EASIL1 + 189                                                          
#define EASIL1_CAMCCC_IRQENABLEFS_IRQ_ENWritefs_irq_en_nomask32                 CAMC_BASE_EASIL1 + 190                                                          
#define EASIL1_CAMCCC_IRQENABLEFS_IRQ_ENSet32                                   CAMC_BASE_EASIL1 + 191                                                          
#define EASIL1_CAMCCC_IRQENABLELE_IRQ_ENRead32                                  CAMC_BASE_EASIL1 + 192                                                          
#define EASIL1_CAMCCC_IRQENABLELE_IRQ_ENReadIsle_irq_en_mask32                  CAMC_BASE_EASIL1 + 193                                                          
#define EASIL1_CAMCCC_IRQENABLELE_IRQ_ENReadIsle_irq_en_nomask32                CAMC_BASE_EASIL1 + 194                                                          
#define EASIL1_CAMCCC_IRQENABLELE_IRQ_ENGet32                                   CAMC_BASE_EASIL1 + 195                                                          
#define EASIL1_CAMCCC_IRQENABLELE_IRQ_ENIsle_irq_en_mask32                      CAMC_BASE_EASIL1 + 196                                                          
#define EASIL1_CAMCCC_IRQENABLELE_IRQ_ENIsle_irq_en_nomask32                    CAMC_BASE_EASIL1 + 197                                                          
#define EASIL1_CAMCCC_IRQENABLELE_IRQ_ENWrite32                                 CAMC_BASE_EASIL1 + 198                                                          
#define EASIL1_CAMCCC_IRQENABLELE_IRQ_ENWritele_irq_en_mask32                   CAMC_BASE_EASIL1 + 199                                                          
#define EASIL1_CAMCCC_IRQENABLELE_IRQ_ENWritele_irq_en_nomask32                 CAMC_BASE_EASIL1 + 200                                                          
#define EASIL1_CAMCCC_IRQENABLELE_IRQ_ENSet32                                   CAMC_BASE_EASIL1 + 201                                                          
#define EASIL1_CAMCCC_IRQENABLELS_IRQ_ENRead32                                  CAMC_BASE_EASIL1 + 202                                                          
#define EASIL1_CAMCCC_IRQENABLELS_IRQ_ENReadIsls_irq_en_mask32                  CAMC_BASE_EASIL1 + 203                                                          
#define EASIL1_CAMCCC_IRQENABLELS_IRQ_ENReadIsls_irq_en_nomask32                CAMC_BASE_EASIL1 + 204                                                          
#define EASIL1_CAMCCC_IRQENABLELS_IRQ_ENGet32                                   CAMC_BASE_EASIL1 + 205                                                          
#define EASIL1_CAMCCC_IRQENABLELS_IRQ_ENIsls_irq_en_mask32                      CAMC_BASE_EASIL1 + 206                                                          
#define EASIL1_CAMCCC_IRQENABLELS_IRQ_ENIsls_irq_en_nomask32                    CAMC_BASE_EASIL1 + 207                                                          
#define EASIL1_CAMCCC_IRQENABLELS_IRQ_ENWrite32                                 CAMC_BASE_EASIL1 + 208                                                          
#define EASIL1_CAMCCC_IRQENABLELS_IRQ_ENWritels_irq_en_mask32                   CAMC_BASE_EASIL1 + 209                                                          
#define EASIL1_CAMCCC_IRQENABLELS_IRQ_ENWritels_irq_en_nomask32                 CAMC_BASE_EASIL1 + 210                                                          
#define EASIL1_CAMCCC_IRQENABLELS_IRQ_ENSet32                                   CAMC_BASE_EASIL1 + 211                                                          
#define EASIL1_CAMCCC_IRQENABLEFE_IRQ_ENRead32                                  CAMC_BASE_EASIL1 + 212                                                          
#define EASIL1_CAMCCC_IRQENABLEFE_IRQ_ENReadIsfe_irq_en_mask32                  CAMC_BASE_EASIL1 + 213                                                          
#define EASIL1_CAMCCC_IRQENABLEFE_IRQ_ENReadIsfe_irq_en_nomask32                CAMC_BASE_EASIL1 + 214                                                          
#define EASIL1_CAMCCC_IRQENABLEFE_IRQ_ENGet32                                   CAMC_BASE_EASIL1 + 215                                                          
#define EASIL1_CAMCCC_IRQENABLEFE_IRQ_ENIsfe_irq_en_mask32                      CAMC_BASE_EASIL1 + 216                                                          
#define EASIL1_CAMCCC_IRQENABLEFE_IRQ_ENIsfe_irq_en_nomask32                    CAMC_BASE_EASIL1 + 217                                                          
#define EASIL1_CAMCCC_IRQENABLEFE_IRQ_ENWrite32                                 CAMC_BASE_EASIL1 + 218