camcaccint.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define EASIL1_CAMCCC_SYSSTATUSReadRegister32                                   CAMC_BASE_EASIL1 + 41                                                           
#define EASIL1_CAMCCC_SYSSTATUSResetDoneRead32                                  CAMC_BASE_EASIL1 + 42                                                           
#define EASIL1_CAMCCC_SYSSTATUSResetDoneReadIsrstOngoing32                      CAMC_BASE_EASIL1 + 43                                                           
#define EASIL1_CAMCCC_SYSSTATUSResetDoneReadIsrstComp32                         CAMC_BASE_EASIL1 + 44                                                           
#define EASIL1_CAMCCC_SYSSTATUSResetDoneGet32                                   CAMC_BASE_EASIL1 + 45                                                           
#define EASIL1_CAMCCC_SYSSTATUSResetDoneIsrstOngoing32                          CAMC_BASE_EASIL1 + 46                                                           
#define EASIL1_CAMCCC_SYSSTATUSResetDoneIsrstComp32                             CAMC_BASE_EASIL1 + 47                                                           
#define EASIL1_CAMCCC_IRQSTATUSReadRegister32                                   CAMC_BASE_EASIL1 + 48                                                           
#define EASIL1_CAMCCC_IRQSTATUSWriteRegister32                                  CAMC_BASE_EASIL1 + 49                                                           
#define EASIL1_CAMCCC_IRQSTATUSFS_IRQRead32                                     CAMC_BASE_EASIL1 + 50                                                           
#define EASIL1_CAMCCC_IRQSTATUSFS_IRQReadIsfase_r32                             CAMC_BASE_EASIL1 + 51                                                           
#define EASIL1_CAMCCC_IRQSTATUSFS_IRQReadIstrue_r32                             CAMC_BASE_EASIL1 + 52                                                           
#define EASIL1_CAMCCC_IRQSTATUSFS_IRQGet32                                      CAMC_BASE_EASIL1 + 53                                                           
#define EASIL1_CAMCCC_IRQSTATUSFS_IRQIsfase_r32                                 CAMC_BASE_EASIL1 + 54                                                           
#define EASIL1_CAMCCC_IRQSTATUSFS_IRQIstrue_r32                                 CAMC_BASE_EASIL1 + 55                                                           
#define EASIL1_CAMCCC_IRQSTATUSFS_IRQWrite32                                    CAMC_BASE_EASIL1 + 56                                                           
#define EASIL1_CAMCCC_IRQSTATUSFS_IRQWritestatUc_w32                            CAMC_BASE_EASIL1 + 57                                                           
#define EASIL1_CAMCCC_IRQSTATUSFS_IRQWritestatrst_w32                           CAMC_BASE_EASIL1 + 58                                                           
#define EASIL1_CAMCCC_IRQSTATUSFS_IRQSet32                                      CAMC_BASE_EASIL1 + 59                                                           
#define EASIL1_CAMCCC_IRQSTATUSLE_IRQRead32                                     CAMC_BASE_EASIL1 + 60                                                           
#define EASIL1_CAMCCC_IRQSTATUSLE_IRQReadIsfase_r32                             CAMC_BASE_EASIL1 + 61                                                           
#define EASIL1_CAMCCC_IRQSTATUSLE_IRQReadIstrue_r32                             CAMC_BASE_EASIL1 + 62                                                           
#define EASIL1_CAMCCC_IRQSTATUSLE_IRQGet32                                      CAMC_BASE_EASIL1 + 63                                                           
#define EASIL1_CAMCCC_IRQSTATUSLE_IRQIsfase_r32                                 CAMC_BASE_EASIL1 + 64                                                           
#define EASIL1_CAMCCC_IRQSTATUSLE_IRQIstrue_r32                                 CAMC_BASE_EASIL1 + 65                                                           
#define EASIL1_CAMCCC_IRQSTATUSLE_IRQWrite32                                    CAMC_BASE_EASIL1 + 66                                                           
#define EASIL1_CAMCCC_IRQSTATUSLE_IRQWritestatUc_w32                            CAMC_BASE_EASIL1 + 67                                                           
#define EASIL1_CAMCCC_IRQSTATUSLE_IRQWritestatrst_w32                           CAMC_BASE_EASIL1 + 68                                                           
#define EASIL1_CAMCCC_IRQSTATUSLE_IRQSet32                                      CAMC_BASE_EASIL1 + 69                                                           
#define EASIL1_CAMCCC_IRQSTATUSLS_IRQRead32                                     CAMC_BASE_EASIL1 + 70                                                           
#define EASIL1_CAMCCC_IRQSTATUSLS_IRQReadIsfase_r32                             CAMC_BASE_EASIL1 + 71                                                           
#define EASIL1_CAMCCC_IRQSTATUSLS_IRQReadIstrue_r32                             CAMC_BASE_EASIL1 + 72                                                           
#define EASIL1_CAMCCC_IRQSTATUSLS_IRQGet32                                      CAMC_BASE_EASIL1 + 73                                                           
#define EASIL1_CAMCCC_IRQSTATUSLS_IRQIsfase_r32                                 CAMC_BASE_EASIL1 + 74                                                           
#define EASIL1_CAMCCC_IRQSTATUSLS_IRQIstrue_r32                                 CAMC_BASE_EASIL1 + 75                                                           
#define EASIL1_CAMCCC_IRQSTATUSLS_IRQWrite32                                    CAMC_BASE_EASIL1 + 76                                                           
#define EASIL1_CAMCCC_IRQSTATUSLS_IRQWritestatUc_w32                            CAMC_BASE_EASIL1 + 77                                                           
#define EASIL1_CAMCCC_IRQSTATUSLS_IRQWritestatrst_w32                           CAMC_BASE_EASIL1 + 78                                                           
#define EASIL1_CAMCCC_IRQSTATUSLS_IRQSet32                                      CAMC_BASE_EASIL1 + 79                                                           
#define EASIL1_CAMCCC_IRQSTATUSFE_IRQRead32                                     CAMC_BASE_EASIL1 + 80                                                           
#define EASIL1_CAMCCC_IRQSTATUSFE_IRQReadIsfase_r32                             CAMC_BASE_EASIL1 + 81                                                           
#define EASIL1_CAMCCC_IRQSTATUSFE_IRQReadIstrue_r32                             CAMC_BASE_EASIL1 + 82                                                           
#define EASIL1_CAMCCC_IRQSTATUSFE_IRQGet32                                      CAMC_BASE_EASIL1 + 83                                                           
#define EASIL1_CAMCCC_IRQSTATUSFE_IRQIsfase_r32                                 CAMC_BASE_EASIL1 + 84                                                           
#define EASIL1_CAMCCC_IRQSTATUSFE_IRQIstrue_r32                                 CAMC_BASE_EASIL1 + 85                                                           
#define EASIL1_CAMCCC_IRQSTATUSFE_IRQWrite32                                    CAMC_BASE_EASIL1 + 86                                                           
#define EASIL1_CAMCCC_IRQSTATUSFE_IRQWritestatUc_w32                            CAMC_BASE_EASIL1 + 87                                                           
#define EASIL1_CAMCCC_IRQSTATUSFE_IRQWritestatrst_w32                           CAMC_BASE_EASIL1 + 88                                                           
#define EASIL1_CAMCCC_IRQSTATUSFE_IRQSet32                                      CAMC_BASE_EASIL1 + 89                                                           
#define EASIL1_CAMCCC_IRQSTATUSFSP_ERR_IRQRead32                                CAMC_BASE_EASIL1 + 90                                                           
#define EASIL1_CAMCCC_IRQSTATUSFSP_ERR_IRQReadIsfase_r32                        CAMC_BASE_EASIL1 + 91                                                           
#define EASIL1_CAMCCC_IRQSTATUSFSP_ERR_IRQReadIstrue_r32                        CAMC_BASE_EASIL1 + 92                                                           
#define EASIL1_CAMCCC_IRQSTATUSFSP_ERR_IRQGet32                                 CAMC_BASE_EASIL1 + 93                                                           
#define EASIL1_CAMCCC_IRQSTATUSFSP_ERR_IRQIsfase_r32                            CAMC_BASE_EASIL1 + 94                                                           
#define EASIL1_CAMCCC_IRQSTATUSFSP_ERR_IRQIstrue_r32                            CAMC_BASE_EASIL1 + 95                                                           
#define EASIL1_CAMCCC_IRQSTATUSFSP_ERR_IRQWrite32                               CAMC_BASE_EASIL1 + 96                                                           
#define EASIL1_CAMCCC_IRQSTATUSFSP_ERR_IRQWritestatUc_w32                       CAMC_BASE_EASIL1 + 97                                                           
#define EASIL1_CAMCCC_IRQSTATUSFSP_ERR_IRQWritestatrst_w32                      CAMC_BASE_EASIL1 + 98                                                           
#define EASIL1_CAMCCC_IRQSTATUSFSP_ERR_IRQSet32                                 CAMC_BASE_EASIL1 + 99                                                           
#define EASIL1_CAMCCC_IRQSTATUSFW_ERR_IRQRead32                                 CAMC_BASE_EASIL1 + 100                                                          
#define EASIL1_CAMCCC_IRQSTATUSFW_ERR_IRQReadIsfase_r32                         CAMC_BASE_EASIL1 + 101                                                          
#define EASIL1_CAMCCC_IRQSTATUSFW_ERR_IRQReadIstrue_r32                         CAMC_BASE_EASIL1 + 102                                                          
#define EASIL1_CAMCCC_IRQSTATUSFW_ERR_IRQGet32                                  CAMC_BASE_EASIL1 + 103                                                          
#define EASIL1_CAMCCC_IRQSTATUSFW_ERR_IRQIsfase_r32                             CAMC_BASE_EASIL1 + 104                                                          
#define EASIL1_CAMCCC_IRQSTATUSFW_ERR_IRQIstrue_r32                             CAMC_BASE_EASIL1 + 105                                                          
#define EASIL1_CAMCCC_IRQSTATUSFW_ERR_IRQWrite32                                CAMC_BASE_EASIL1 + 106                                                          
#define EASIL1_CAMCCC_IRQSTATUSFW_ERR_IRQWritestatUc_w32                        CAMC_BASE_EASIL1 + 107                                                          
#define EASIL1_CAMCCC_IRQSTATUSFW_ERR_IRQWritestatrst_w32                       CAMC_BASE_EASIL1 + 108                                                          
#define EASIL1_CAMCCC_IRQSTATUSFW_ERR_IRQSet32                                  CAMC_BASE_EASIL1 + 109                                                          
#define EASIL1_CAMCCC_IRQSTATUSFSC_ERR_IRQRead32                                CAMC_BASE_EASIL1 + 110                                                          
#define EASIL1_CAMCCC_IRQSTATUSFSC_ERR_IRQReadIsfase_r32                        CAMC_BASE_EASIL1 + 111                                                          
#define EASIL1_CAMCCC_IRQSTATUSFSC_ERR_IRQReadIstrue_r32                        CAMC_BASE_EASIL1 + 112                                                          
#define EASIL1_CAMCCC_IRQSTATUSFSC_ERR_IRQGet32                                 CAMC_BASE_EASIL1 + 113                                                          
#define EASIL1_CAMCCC_IRQSTATUSFSC_ERR_IRQIsfase_r32                            CAMC_BASE_EASIL1 + 114                                                          
#define EASIL1_CAMCCC_IRQSTATUSFSC_ERR_IRQIstrue_r32                            CAMC_BASE_EASIL1 + 115                                                          
#define EASIL1_CAMCCC_IRQSTATUSFSC_ERR_IRQWrite32                               CAMC_BASE_EASIL1 + 116                                                          
#define EASIL1_CAMCCC_IRQSTATUSFSC_ERR_IRQWritestatUc_w32                       CAMC_BASE_EASIL1 + 117                                                          
#define EASIL1_CAMCCC_IRQSTATUSFSC_ERR_IRQWritestatrst_w32                      CAMC_BASE_EASIL1 + 118                                                          
#define EASIL1_CAMCCC_IRQSTATUSFSC_ERR_IRQSet32                                 CAMC_BASE_EASIL1 + 119                                                          
#define EASIL1_CAMCCC_IRQSTATUSSSC_ERR_IRQRead32                                CAMC_BASE_EASIL1 + 120                                                          
#define EASIL1_CAMCCC_IRQSTATUSSSC_ERR_IRQReadIsfase_r32                        CAMC_BASE_EASIL1 + 121                                                          
#define EASIL1_CAMCCC_IRQSTATUSSSC_ERR_IRQReadIstrue_r32                        CAMC_BASE_EASIL1 + 122                                                          
#define EASIL1_CAMCCC_IRQSTATUSSSC_ERR_IRQGet32                                 CAMC_BASE_EASIL1 + 123                                                          
#define EASIL1_CAMCCC_IRQSTATUSSSC_ERR_IRQIsfase_r32                            CAMC_BASE_EASIL1 + 124                                                          
#define EASIL1_CAMCCC_IRQSTATUSSSC_ERR_IRQIstrue_r32                            CAMC_BASE_EASIL1 + 125                                                          
#define EASIL1_CAMCCC_IRQSTATUSSSC_ERR_IRQWrite32                               CAMC_BASE_EASIL1 + 126                                                          
#define EASIL1_CAMCCC_IRQSTATUSSSC_ERR_IRQWritestatUc_w32                       CAMC_BASE_EASIL1 + 127                                                          
#define EASIL1_CAMCCC_IRQSTATUSSSC_ERR_IRQWritestatrst_w32                      CAMC_BASE_EASIL1 + 128                                                          
#define EASIL1_CAMCCC_IRQSTATUSSSC_ERR_IRQSet32                                 CAMC_BASE_EASIL1 + 129