easibase.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/* ============================================================================
*
*            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
*
*   Property of Texas Instruments
*   For Unrestricted Internal Use Only 
*   Unauthorized reproduction and/or distribution is strictly prohibited.
*   This product is protected under copyright law and trade secret law as an unpublished work.
*   Created 2003, (C) Copyright 2003 Texas Instruments.  All rights reserved.
*
*   Component:     Easi Base Value Defines used by both Easi C and Easi checker
*    
*   Filename:      EasiBase.h           
*    
*   Description:   Header file required by beach auto generated code
*
*   Domain:        ARM11
*
*    
* =============================================================================
*/
#ifndef __EASIBASE_H
#define __EASIBASE_H

/* ============================================================================
* INCLUDE FILES (only if necessary)
* =============================================================================
*/
#ifdef __cplusplus
extern "C"
{
#endif

/* ============================================================================
* EXPORTED DEFINITIONS
* =============================================================================
*/

/* ----------------------------------------------------------------------------
* DEFINE:        ****_BASE_ID       
*
* DESCRIPTION:  These are registser BASE IDs that will be used to identify 
*               errors when doing the EASI-Checker register tests
*
* NOTE:         The values of these defines will be defined at a later stage. TBD
*
* -----------------------------------------------------------------------------
*/


#define AES1_BASE_ID 0
#define BCM1_BASE_ID   0
#define C2CF1_BASE_ID 0
#define CAMC1_BASE_ID 0
#define CDMA1_BASE_ID 0
#define CMMU1_BASE_ID  0
#define CAM1_BASE_ID  0
#define D3D1_BASE_ID 0
#define DDMA1_BASE_ID  0
#define DISC1_BASE_ID 0
#define DISS1_BASE_ID 0
#define DSPF1_BASE_ID 0
#define DSS1_BASE_ID 0
#define EAC1_BASE_ID 0
#define ETB1_BASE_ID 0
#define FAC1_BASE_ID 0
#define GDD1_BASE_ID 0
#define GFX1_BASE_ID  0
#define GPIO1_BASE_ID 0
#define GPIO2_BASE_ID 0
#define GPIO3_BASE_ID 0
#define GPIO4_BASE_ID 0
#define GPMC1_BASE_ID 0
#define GPMF1_BASE_ID 0
#define GPT10_BASE_ID 0
#define GPT11_BASE_ID 0
#define GPT12_BASE_ID 0
#define GPT1_BASE_ID 0
#define GPT2_BASE_ID 0
#define GPT3_BASE_ID 0
#define GPT4_BASE_ID 0
#define GPT5_BASE_ID 0
#define GPT6_BASE_ID 0
#define GPT7_BASE_ID 0
#define GPT8_BASE_ID 0
#define GPT9_BASE_ID 0
#define HDQW1_BASE_ID 0
#define I2C1_BASE_ID 0
#define I2C2_BASE_ID 0
#define IM1_BASE_ID 0
#define IM2_BASE_ID 0
#define IM3_BASE_ID 0
#define IM4_BASE_ID 0
#define IM5_BASE_ID 0
#define IM6_BASE_ID 0
#define IM7_BASE_ID 0
#define IM8_BASE_ID 0
#define IMA1_BASE_ID 0
#define IMTM1_BASE_ID 0
#define IMTM2_BASE_ID 0
#define IMTMA1_BASE_ID 0
#define INTC1_BASE_ID 0
#define INTC2_BASE_ID 0
#define IPI1_BASE_ID 0
#define IVA1_BASE_ID 0
#define IVAF1_BASE_ID 0
#define JTAG1_BASE_ID  0
#define L4CON1_BASE_ID 0
#define L4IA1_BASE_ID 0
#define L4LA1_BASE_ID 0
#define L4TA10_BASE_ID 0
#define L4TA11_BASE_ID 0
#define L4TA12_BASE_ID 0
#define L4TA13_BASE_ID 0
#define L4TA14_BASE_ID 0
#define L4TA15_BASE_ID 0
#define L4TA16_BASE_ID 0
#define L4TA17_BASE_ID 0
#define L4TA18_BASE_ID 0
#define L4TA19_BASE_ID 0
#define L4TA1_BASE_ID 0
#define L4TA20_BASE_ID 0
#define L4TA21_BASE_ID 0
#define L4TA22_BASE_ID 0
#define L4TA23_BASE_ID 0
#define L4TA24_BASE_ID 0
#define L4TA25_BASE_ID 0
#define L4TA26_BASE_ID 0
#define L4TA27_BASE_ID 0
#define L4TA28_BASE_ID 0
#define L4TA29_BASE_ID 0
#define L4TA2_BASE_ID 0
#define L4TA30_BASE_ID 0
#define L4TA31_BASE_ID 0
#define L4TA32_BASE_ID 0
#define L4TA33_BASE_ID 0
#define L4TA34_BASE_ID 0
#define L4TA35_BASE_ID 0
#define L4TA36_BASE_ID 0
#define L4TA37_BASE_ID 0
#define L4TA38_BASE_ID 0
#define L4TA39_BASE_ID 0
#define L4TA3_BASE_ID 0
#define L4TA40_BASE_ID 0
#define L4TA41_BASE_ID 0
#define L4TA42_BASE_ID 0
#define L4TA43_BASE_ID 0
#define L4TA44_BASE_ID 0
#define L4TA45_BASE_ID 0
#define L4TA46_BASE_ID 0
#define L4TA47_BASE_ID 0
#define L4TA48_BASE_ID 0
#define L4TA49_BASE_ID 0
#define L4TA4_BASE_ID 0
#define L4TA50_BASE_ID 0
#define L4TA51_BASE_ID 0
#define L4TA52_BASE_ID 0
#define L4TA53_BASE_ID 0
#define L4TA54_BASE_ID 0
#define L4TA55_BASE_ID 0
#define L4TA56_BASE_ID 0
#define L4TA57_BASE_ID 0
#define L4TA58_BASE_ID 0
#define L4TA5_BASE_ID 0
#define L4TA6_BASE_ID 0
#define L4TA7_BASE_ID 0
#define L4TA8_BASE_ID 0
#define L4TA9_BASE_ID 0
#define LRCR1_BASE_ID 0
#define LRCR2_BASE_ID 0
#define LRCS1_BASE_ID 0
#define LRCS2_BASE_ID 0
#define MBSP1_BASE_ID 0
#define MBSP2_BASE_ID 0
#define MCSPI1_BASE_ID 0
#define MCSPI2_BASE_ID 0
#define MLB1_BASE_ID 0
#define MMU1_BASE_ID 0
#define MMU2_BASE_ID 0
#define MSDI1_BASE_ID 0
#define MSP1_BASE_ID 0
#define MSPPRO_BASE_ID 0
#define MSPRO1_BASE_ID 0
#define OSPL1_BASE_ID 0
#define OSPL2_BASE_ID 0
#define OSPL3_BASE_ID 0
#define OSPL4_BASE_ID 0
#define PBUF1_BASE_ID  0
#define PDMA1_BASE_ID 0
#define PKA1_BASE_ID 0
#define PRCM1_BASE_ID 0
#define PRCM_BASE_ID 0
#define RAMF1_BASE_ID 0
#define RFBI1_BASE_ID 0
#define RNG1_BASE_ID 0
#define ROMF1_BASE_ID 0
#define SDMA1_BASE_ID 0
#define SDRC1_BASE_ID 0
#define SHAM1_BASE_ID 0
#define SMS1_BASE_ID 0
#define SSI1_BASE_ID 0
#define SSR1_BASE_ID 0
#define SSR2_BASE_ID  0
#define SST1_BASE_ID 0
#define SST2_BASE_ID  0
#define ST1_BASE_ID 0
#define SWT1_BASE_ID  0
#define SYSC1_BASE_ID 0
#define T32K1_BASE_ID 0
#define TM1_BASE_ID 0
#define TM2_BASE_ID 0
#define TM3_BASE_ID 0
#define TM4_BASE_ID 0
#define TM5_BASE_ID 0
#define TM6_BASE_ID 0
#define TM7_BASE_ID 0
#define TMA1_BASE_ID 0
#define TML1_BASE_ID 0
#define USBOT1_BASE_ID 0
#define V20C1_BASE_ID  0
#define V20W1_BASE_ID  0
#define VENC1_BASE_ID  0
#define WDT1_BASE_ID 0
#define WDT2_BASE_ID 0
#define WDT3_BASE_ID 0
#define WDT4_BASE_ID 0
#define WOSP1_BASE_ID  0
#define WTR1_BASE_ID 0
#define WTR2_BASE_ID 0
#define WTR3_BASE_ID 0
#define WTR4_BASE_ID 0
#define XTI1_BASE_ID 0

#define IMTMA1_BASE_ID 0
#define UMA1_BASE_ID 0

#define L4TAO1_BASE_ID 0
#define L4TAO2_BASE_ID 0
#define L4TAO3_BASE_ID 0
#define L4TAO4_BASE_ID 0
#define L4TAO5_BASE_ID 0
#define L4TAO6_BASE_ID 0
#define L4TAO7_BASE_ID 0
#define L4TAO8_BASE_ID 0
#define L4TAO9_BASE_ID 0
#define L4TAO10_BASE_ID 0
#define L4TAO11_BASE_ID 0
#define L4TAO12_BASE_ID 0
#define L4TAO13_BASE_ID 0
#define L4TAO14_BASE_ID 0


/* The UART is an exception as the beach functions
   have been hand written */
#define UART_BASE_ID 0
/* The MG is an exception as the beach functions
   have been hand written */
#define MG1_BASE_ID 0
#define MGW1_BASE_ID 0

/* ----------------------------------------------------------------------------
* DEFINE: ***_BASE_EASIL1       
*
* DESCRIPTION:  These are registser BASE EASIl1 numbers that can be used to 
*               identify what EASI C functions have been called.
*
* NOTE:         The values of these defines will be defined at a later stage. TBD
*
* -----------------------------------------------------------------------------
*/



#define AES_BASE_EASIL1 0
#define BCM_BASE_EASIL1   0
#define C2CF_BASE_EASIL1 0
#define CAMC_BASE_EASIL1 0
#define CDMA_BASE_EASIL1 0
#define CMMU_BASE_EASIL1 0
#define CAM_BASE_EASIL1 0
#define D3D_BASE_EASIL1 0
#define DDMA_BASE_EASIL1  0
#define DISC_BASE_EASIL1 0
#define DISS_BASE_EASIL1 0
#define DSPF_BASE_EASIL1 0
#define DSS_BASE_EASIL1 0
#define EAC_BASE_EASIL1 0
#define ETB_BASE_EASIL1 0
#define FAC_BASE_EASIL1 0
#define GDD_BASE_EASIL1 0
#define GFX_BASE_EASIL1  0
#define GPIO_BASE_EASIL1 0
#define GPMC_BASE_EASIL1 0
#define GPMF_BASE_EASIL1 0
#define GPT_BASE_EASIL1 0
#define HDQW_BASE_EASIL1 0
#define I2C1_BASE_EASIL1 0
#define I2C2_BASE_EASIL1 0
#define IMA_BASE_EASIL1  0
#define IMTM_BASE_EASIL1  0
#define IMTMA_BASE_EASIL1  0
#define IM_BASE_EASIL1  0
#define INTC1_BASE_EASIL1 0
#define INTC2_BASE_EASIL1 0
#define IPI_BASE_EASIL1 0
#define IVAF_BASE_EASIL1  0
#define IVA_BASE_EASIL1 0
#define JTAG_BASE_EASIL1  0
#define L4CON_BASE_EASIL1 0
#define L4IA_BASE_EASIL1 0
#define L4LA_BASE_EASIL1 0
#define L4TAO_BASE_EASIL1 0
#define L4TA_BASE_EASIL1 0
#define LRCR_BASE_EASIL1  0
#define LRCS_BASE_EASIL1  0
#define MBSP2_BASE_EASIL1 0
#define MBSP_BASE_EASIL1 0
#define MCSPI_BASE_EASIL1 0
#define MG1_BASE_EASIL1 0
#define MGW1_BASE_EASIL1 0
#define MLB_BASE_EASIL1 0
#define MMU1_BASE_EASIL1 0
#define MSDI_BASE_EASIL1 0
#define MSP1_BASE_EASIL1 0
#define OSPL_BASE_EASIL1 0
#define PBUF_BASE_EASIL1  0
#define PDMA_BASE_EASIL1 0
#define PKA1_BASE_EASIL1 0
#define PRCM_BASE_EASIL1 0
#define RAMF_BASE_EASIL1  0
#define RFBI_BASE_EASIL1 0
#define RNG_BASE_EASIL1 0
#define ROMF_BASE_EASIL1  0
#define SDMA_BASE_EASIL1 0
#define SDRC_BASE_EASIL1 0
#define SHAM_BASE_EASIL1 0
#define SMS_BASE_EASIL1 0
#define SSI_BASE_EASIL1 0
#define SSR_BASE_EASIL1 0
#define SST_BASE_EASIL1 0
#define ST_BASE_EASIL1 0
#define SWT_BASE_EASIL1 0
#define SYSC_BASE_EASIL1 0
#define T32K_BASE_EASIL1 0
#define TML_BASE_EASIL1  0
#define TM_BASE_EASIL1  0
#define TMA_BASE_EASIL1  0
#define UART_BASE_EASIL1 0
#define USBOT_BASE_EASIL1 0
#define V20C_BASE_EASIL1 0
#define V20W_BASE_EASIL1 0
#define VENC_BASE_EASIL1 0
#define WDT1_BASE_EASIL1 0
#define WOSP_BASE_EASIL1  0
#define WTR_BASE_EASIL1 0
#define XTI_BASE_EASIL1 0
#define IMTMA_BASE_EASIL1 0
#define UMA_BASE_EASIL1 0



/* ============================================================================
* EXPORTED TYPES
* =============================================================================
*/


/* ============================================================================
* EXPORTED VARIABLES
* =============================================================================
*/


/* ============================================================================
* EXPORTED FUNCTIONS/MACROS
* =============================================================================
*/

#ifdef __cplusplus
}
#endif
#endif	/* __EASIBASE_H */