📄 configuration-generic.h.s
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TB_ETMMMD CONFIG_SETA TB_BASE + 0x84
TB_ETMTRIG CONFIG_SETA TB_BASE + 0x88
TB_ETMEXTIN CONFIG_SETA TB_BASE + 0x8C
TB_ETMMMD1 CONFIG_SETA TB_BASE + 0x90
TB_ETMMMD2 CONFIG_SETA TB_BASE + 0x94
TB_ETMMMD3 CONFIG_SETA TB_BASE + 0x98
TB_ETMMMD4 CONFIG_SETA TB_BASE + 0x9C
TB_ETMCYCACC CONFIG_SETA TB_BASE + 0xA0
SUPPORTS_BYTE_SINGLEABORT CONFIG_SETL {TRUE}
;redundant Trickbox variables that need to be removed sometime
TrickBox_base CONFIG_SETA TB_BASE
TubeAd CONFIG_SETA TB_TUBE
LowAbortReg CONFIG_SETA TB_LOABORT
HighAbortReg CONFIG_SETA TB_HIABORT
SWIAccelAd CONFIG_SETA TB_SWIACCEL
CLibEmul CONFIG_SETA TB_DEMONSWI
SimStopAd CONFIG_SETA 0x030000C0
MEND
;--------------------------------------------------------------------------------
; Macro: CACHE_CFG
;
; Function: Sets up default values for devices having caches
;--------------------------------------------------------------------------------
MACRO
CACHE_CFG
HAS_CACHES CONFIG_SETL {TRUE}
; Cache ID type
CACHE_TYPE CONFIG_SETA 0
; current ICache mode: one of C, NC
ICACHE_MODE CONFIG_SETS "NC"
; current DCache mode: one of CB, CNB, NCB, NCNB
DCACHE_MODE CONFIG_SETS "NCNB"
WRITE_BACK CONFIG_SETL {TRUE}
WRITE_THRO CONFIG_SETL {TRUE}
LOCKDOWN CONFIG_SETL {TRUE}
SUPPORTS_INV_IND CONFIG_SETL {FALSE}
SUPPORTS_INV_ID CONFIG_SETL {TRUE}
CACHEABLE_SWPS CONFIG_SETL {TRUE}
WRITES_ALWAYS_UPDATE_CACHE CONFIG_SETL {FALSE}
UNEXPECTED_HITS CONFIG_SETL {FALSE}
CACHE_NUM_COLUMN CONFIG_SETA 32
CACHE_LINE_BOUNDARY CONFIG_SETA 32
CACHE_NUM_COLUMN_BITS CONFIG_SETA 5
LOCKDOWN_BASE_LSB CONFIG_SETA 26
LOCKDOWN_LOCK_BIT CONFIG_SETA 0
INV_IND_OP2 CONFIG_SETA 2
INV_VA_OP2 CONFIG_SETA 1
WBUFFER_SIZE CONFIG_SETA 16
MEND
;--------------------------------------------------------------------------------
; Macro: MMU_CFG
;
; Function: Sets up default values for devices having MMU's
;--------------------------------------------------------------------------------
MACRO
MMU_CFG
HAS_MMU CONFIG_SETL {TRUE}
MMU_ENABLED CONFIG_SETL {FALSE}
TINY_PAGES CONFIG_SETL {FALSE}
FAR_ALWAYS_UPDATES CONFIG_SETL {FALSE}
UNIFIED_PU CONFIG_SETL {FALSE}
MEND
;--------------------------------------------------------------------------------
; Macro: PU_CFG
;
; Function: Sets up default values for devices having Protection Units
;--------------------------------------------------------------------------------
MACRO
PU_CFG
HAS_PU CONFIG_SETL {TRUE}
MMU_ENABLED CONFIG_SETL {FALSE}
MEND
;*****************************************************************************
;Index
;=====
;a) Target
;b) Architecture
;c) Initialisation
;d) Cache
;e) Coprocessor
;f) Interrupts
;g) Execution environment
;h) Hardware environment
;i) Aborts
;
;a) Target
;=========
;TARGET ;Build target
; ;e.g. ARM940TD
;DEVICE_REV ;Revision of target
; ;e.g. 1, 2..
;KNOWN_TARGET ;Is TARGET known
; ;TRUE/FALSE
;b) Architecture
;===============
;PROC ;Processor type of target
; ;e.g. ARM6/ARM8; usually set to TARGET
;ARM_ARCH ;ARM architecture version of processor
; ;e.g. 3/4
;SUPPORTS_26BIT ;Does core support 26-bit architectures
; ;TRUE/FALSE
;SUPPORTS_THUMB ;Does the core support the thumb instruction set
; ;TRUE/FALSE
;HARVARD ;Harvard architecture
; ;TRUE/FALSE
;COHERENT_ISTREAM ;Used to indicate whether the instr
; ;stream is identical to the Data
; ;stream (excluding pipeline effects)
; ;ie Harvard Architecture/Prefetch etc
; ;TRUE/FALSE
;PC_FULL ;Are the bottom two bits of the PC
; ;included in Data processing ops.
; ;TRUE/FALSE
;PC_BIT1SET ;Can bit 1 can be set in PC.
; ;TRUE/FALSE
;PC_OFFSET ;the offset of r15, from the current
; ;instruction, when stored using STR/STM
; ;e.g. 8/12
;c) Initialisation
;=================
;INITIALISE ;Flag used to state whether the core
; ;should be initialised or not. The
; ;exact form of initialisation depends
; ;on the processor target, and is
; ;detailed at the end of the file
; ;TRUE/FALSE
;d) Cache (for cached processor)
;===============================
;LOCKDOWN ;Does the cache support Lock Down.
; ;TRUE/FALSE
;WRITE_BACK ;Write back cache rather than write through
; ;TRUE/FALSE
;CACHE_LINE_BOUNDARY ;Number of bytes in a cache line
; ;e.g. 16/32
;CACHE_NUM_COLUMN ;Number of bytes in a cache line
; ;i.e. CACHE_LINE_BOUNDARY
;CACHE_NUM_COLUMN_BITS ;log 2 CACHE_NUM_COLUMN for ALIGN declarations
;
;CACHE_NUM_ROW ;Number of rows in cache
;
;CACHE_SIZE ;Number of bytes in cache
; ;Computed by CACHE_LINE_BOUNDARY * CACHE_NUM_ROWS
;e) Coprocessor
;==============
;COPROC_SUPPORT ;Does target support a coprocessor (STC,LDC etc)
; ;TRUE/FALSE
;CP_BUSY_WAIT ;Can the processor busy wait on a
; ;co-processor instruction
; ;TRUE/FALSE
;;Set up coprocessor registers (e.g. CP p0)
;CP_BOUNCE ;Bounce coprocessor access
;CP_BOUNCE_D ;Bounce
;CP_BOUNCE_E ;Bounce
;CP_BUSYWAIT ;Coprocessor busy wait delay
;CP_BUSYWAIT_D ;Coprocessor busy wait delay
;CP_BUSYWAIT_E ;Coprocessor busy wait delay
;CP_PRIVILEGED ;Coprocessor access privileged
;CP_STANDARD ;Coprocessor access unprivileged
;CP_TRICKBOX ;Coprocessor version of "trick box"
;CP_SYSTEM ;Standard system coprocessor
;f) Interrupts
;=============
;INTERRUPT_CONFIG ;Interrupt configuration
; ;[MEMORY_MAPPED/COPROC/EBSARM/NONE]
;g) Execution Environment
;========================
;CLibEmul ;Full C library emulation address
; ;e.g. CONFIG_SETA 0x60000000
;TubeAd ;Tube address
; ;e.g. CONFIG_SETA 0x03000000
;TrickBox_base ;Trickbox base address
; ;e.g. CONFIG_SETA 0x03000000
;LIBRARY ;C library type, presently either Demon or Angel.
; ;If Angel is selected then the variables
; ;ANGEL_SWI_ARM and ANGEL_SWI_THUMB must be set.
; ;[DEMON|ANGEL]
;SWI_SUPPORT ;Full or validation SWI support.
; ;For validation emulation, only messaging and some
; ;peripheral SWI's work.
; ;Full SWI emulation is slower and needs
; ;the modelgen SWI emulator to be linked into the
; ;HDL world.
; ;If full SWI emulation is selected CLibEmul must be
; ;set.
; ;[FULL|VALIDATION]
;ANGEL_SWI_ARM ;Angel SWI number in ARM mode. Normally: 0x123456
;ANGEL_SWI_THUMB ;Angel SWI number in Thumb mode. Normally: 0xab
;ENVIRONMENT ;Indicates the type of simulation environment
; ;[HDL|BOARD|EASY]
;STDOUT ;Select the output method, either via the tube or
; ;the comms port.
; ;Tube: Output characters via the tube.
; ;Comms: Output characters via the PID boards
; ;comms port
; ;[COMMS|TUBE]
;FULL_MEMORY_MODEL ;Indicates whether the processor
; ;supports a full dynamically allocated
; ;memory model
; ;TRUE/FALSE
;BASE_ORG ;****Do not use. For backwards compatability only****
; ;Base Origin used for assembly &
; ;linking
; ;e.g. 0x0000/0x8000
;SIMULATION_ENV ;****Do not use. For backwards compatability only****
; ;Used to indicate the type of simulation
; ;environment [DEMON|STD]
;h) Hardware Environment
;=======================
;PROG32 ;Tie PROG32 high (TRUE=32bit mode, FALSE 26bit mode)
; ;TRUE/FALSE
;i) Aborts
;=========
;AbortStart ;Abort start address
; ;e.g. CONFIG_SETA 0x00700000
;BadAddress ;Abort on address
; ;e.g. CONFIG_SETA 0x01000000
;NPabort ;Non-privileged abort
; ;e.g. CONFIG_SETA 0x01500000
;SWPabort ;Swap abort
; ;e.g. CONFIG_SETA 0x01600000
;AbortEnd ;End address of abort region
; ;e.g. CONFIG_SETA 0x01A00000
;BASE_RESTORATION_SINGLE ;Does the processor restore the
; ;original base register when a
; ;single memory access aborts
; ;TRUE/FALSE
;BASE_RESTORATION_MULTI ;Does the processor restore the
; ;original base register when a
; ;multiple memory access aborts
; ;TRUE/FALSE
;STM_WB_REG_IN_LIST ;What is the value in memory equal to when an STM
; ;with writeback is performed and the base register
; ;is in the register list? "Final Value" indicates
; ;the base register's value after the STM is equal
; ;to the value in memory, "Initial Value" indicates
; ;the base register's value before the STM is equal to
; ;the value in memory. NOTE: The ARM ARM defines
; ;this situation as UNPREDICTABLE.
;********************************************************************************
END
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