wcdma_enc.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define             COUNT_reg_write_RD_MASK    0xFFFFFFFF

#define             COUNT_reg_write_WR_MASK    0xFFFFFFFF


#define             CK0_reg_write_RD_MASK    0xFFFFFFFF

#define             CK0_reg_write_WR_MASK    0xFFFFFFFF


#define             CK1_reg_write_RD_MASK    0xFFFFFFFF

#define             CK1_reg_write_WR_MASK    0xFFFFFFFF


#define             CK2_reg_write_RD_MASK    0xFFFFFFFF

#define             CK2_reg_write_WR_MASK    0xFFFFFFFF


#define             CK3_reg_write_RD_MASK    0xFFFFFFFF

#define             CK3_reg_write_WR_MASK    0xFFFFFFFF


#define             DIRECTION_BEARER_LENGTH_reg_write_RD_MASK    0xFFFF1F01

#define             DIRECTION_BEARER_LENGTH_reg_write_WR_MASK    0xFFFF1F01


#define             FRESH_reg_write_RD_MASK    0xFFFFFFFF

#define             FRESH_reg_write_WR_MASK    0xFFFFFFFF


#define             IK0_reg_write_RD_MASK    0xFFFFFFFF

#define             IK0_reg_write_WR_MASK    0xFFFFFFFF


#define             IK1_reg_write_RD_MASK    0xFFFFFFFF

#define             IK1_reg_write_WR_MASK    0xFFFFFFFF


#define             IK2_reg_write_RD_MASK    0xFFFFFFFF

#define             IK2_reg_write_WR_MASK    0xFFFFFFFF


#define             IK3_reg_write_RD_MASK    0xFFFFFFFF

#define             IK3_reg_write_WR_MASK    0xFFFFFFFF


#define             COUNT_reg_read_RD_MASK    0xFFFFFFFF

#define             COUNT_reg_read_WR_MASK    0xFFFFFFFF


#define             CK0_reg_read_RD_MASK    0xFFFFFFFF

#define             CK0_reg_read_WR_MASK    0xFFFFFFFF


#define             CK1_reg_read_RD_MASK    0xFFFFFFFF

#define             CK1_reg_read_WR_MASK    0xFFFFFFFF


#define             CK2_reg_read_RD_MASK    0xFFFFFFFF

#define             CK2_reg_read_WR_MASK    0xFFFFFFFF


#define             CK3_reg_read_RD_MASK    0xFFFFFFFF

#define             CK3_reg_read_WR_MASK    0xFFFFFFFF


#define             DIRECTION_BEARER_LENGTH_reg_read_RD_MASK    0xFFFF1F01

#define             DIRECTION_BEARER_LENGTH_reg_read_WR_MASK    0xFFFF1F01


#define             FRESH_reg_read_RD_MASK    0xFFFFFFFF

#define             FRESH_reg_read_WR_MASK    0xFFFFFFFF


#define             IK0_reg_read_RD_MASK    0xFFFFFFFF

#define             IK0_reg_read_WR_MASK    0xFFFFFFFF


#define             IK1_reg_read_RD_MASK    0xFFFFFFFF

#define             IK1_reg_read_WR_MASK    0xFFFFFFFF


#define             IK2_reg_read_RD_MASK    0xFFFFFFFF

#define             IK2_reg_read_WR_MASK    0xFFFFFFFF


#define             IK3_reg_read_RD_MASK    0xFFFFFFFF

#define             IK3_reg_read_WR_MASK    0xFFFFFFFF


#define             Init_f8_RD_MASK    0x00000000

#define             Init_f8_WR_MASK    0xFFFFFFFF


#define             Init_f9_RD_MASK    0x00000000

#define             Init_f9_WR_MASK    0xFFFFFFFF

//RAM Locations


//Input_Buffer_Memory_write_0
#define           Input_Buffer_Memory_write_0_OFFSET           0x0
#define           Input_Buffer_Memory_write_0                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Input_Buffer_Memory_write_0_OFFSET) << 2))

#define             Input_Buffer_Memory_write_0_RD_MASK    0xFFFFFFFF
#define             Input_Buffer_Memory_write_0_WR_MASK    0xFFFFFFFF
//-------------------------
//Input_Buffer_Memory_write_1
#define           Input_Buffer_Memory_write_1_OFFSET           0x1
#define           Input_Buffer_Memory_write_1                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Input_Buffer_Memory_write_1_OFFSET) << 2))

#define             Input_Buffer_Memory_write_1_RD_MASK    0xFFFFFFFF
#define             Input_Buffer_Memory_write_1_WR_MASK    0xFFFFFFFF
//-------------------------
//Input_Buffer_Memory_write_2
#define           Input_Buffer_Memory_write_2_OFFSET           0x2
#define           Input_Buffer_Memory_write_2                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Input_Buffer_Memory_write_2_OFFSET) << 2))

#define             Input_Buffer_Memory_write_2_RD_MASK    0xFFFFFFFF
#define             Input_Buffer_Memory_write_2_WR_MASK    0xFFFFFFFF
//Input_Buffer_Memory_write_3
#define           Input_Buffer_Memory_write_3_OFFSET           0x3
#define           Input_Buffer_Memory_write_3                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Input_Buffer_Memory_write_3_OFFSET) << 2))

#define             Input_Buffer_Memory_write_3_RD_MASK    0xFFFFFFFF
#define             Input_Buffer_Memory_write_3_WR_MASK    0xFFFFFFFF

//Input_Buffer_Memory_write_79
#define           Input_Buffer_Memory_write_79_OFFSET           0x4f
#define           Input_Buffer_Memory_write_79                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Input_Buffer_Memory_write_79_OFFSET) << 2))

#define             Input_Buffer_Memory_write_79_RD_MASK    0xFFFFFFFF
#define             Input_Buffer_Memory_write_79_WR_MASK    0xFFFFFFFF

//RAM Locations


//Output_Buffer_Memory_read_0
#define           Output_Buffer_Memory_read_0_OFFSET           0x200
#define           Output_Buffer_Memory_read_0                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Output_Buffer_Memory_read_0_OFFSET) << 2))

#define             Output_Buffer_Memory_read_0_RD_MASK    0xFFFFFFFF
#define             Output_Buffer_Memory_read_0_WR_MASK    0xFFFFFFFF
//-------------------------
//Output_Buffer_Memory_read_1
#define           Output_Buffer_Memory_read_1_OFFSET           0x201
#define           Output_Buffer_Memory_read_1                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Output_Buffer_Memory_read_1_OFFSET) << 2))

#define             Output_Buffer_Memory_read_1_RD_MASK    0xFFFFFFFF
#define             Output_Buffer_Memory_read_1_WR_MASK    0xFFFFFFFF

//Output_Buffer_Memory_read_79
#define           Output_Buffer_Memory_read_79_OFFSET           0x24f
#define           Output_Buffer_Memory_read_79                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Output_Buffer_Memory_read_79_OFFSET) << 2))

#define             Output_Buffer_Memory_read_79_RD_MASK    0xFFFFFFFF
#define             Output_Buffer_Memory_read_79_WR_MASK    0xFFFFFFFF

//RAM Locations


//Input_Buffer_Memory_read_0
#define           Input_Buffer_Memory_read_0_OFFSET           0x600
#define           Input_Buffer_Memory_read_0                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Input_Buffer_Memory_read_0_OFFSET) << 2))

#define             Input_Buffer_Memory_read_0_RD_MASK    0xFFFFFFFF
#define             Input_Buffer_Memory_read_0_WR_MASK    0xFFFFFFFF
//-------------------------
//Input_Buffer_Memory_read_1
#define           Input_Buffer_Memory_read_1_OFFSET           0x601
#define           Input_Buffer_Memory_read_1                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Input_Buffer_Memory_read_1_OFFSET) << 2))

#define             Input_Buffer_Memory_read_1_RD_MASK    0xFFFFFFFF
#define             Input_Buffer_Memory_read_1_WR_MASK    0xFFFFFFFF
//-------------------------
//-------------------------
//Input_Buffer_Memory_read_2
#define           Input_Buffer_Memory_read_2_OFFSET           0x602
#define           Input_Buffer_Memory_read_2                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Input_Buffer_Memory_read_2_OFFSET) << 2))

#define             Input_Buffer_Memory_read_2_RD_MASK    0xFFFFFFFF
#define             Input_Buffer_Memory_read_2_WR_MASK    0xFFFFFFFF
//-------------------------
//-------------------------
//Input_Buffer_Memory_read_3
#define           Input_Buffer_Memory_read_3_OFFSET           0x603
#define           Input_Buffer_Memory_read_3                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Input_Buffer_Memory_read_3_OFFSET) << 2))

#define             Input_Buffer_Memory_read_3_RD_MASK    0xFFFFFFFF
#define             Input_Buffer_Memory_read_3_WR_MASK    0xFFFFFFFF
//-------------------------

//Input_Buffer_Memory_read_79
#define           Input_Buffer_Memory_read_79_OFFSET           0x64f
#define           Input_Buffer_Memory_read_79                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Input_Buffer_Memory_read_79_OFFSET) << 2))

#define             Input_Buffer_Memory_read_79_RD_MASK    0xFFFFFFFF
#define             Input_Buffer_Memory_read_79_WR_MASK    0xFFFFFFFF

//RAM Locations


//Output_Buffer_Memory_write_0
#define           Output_Buffer_Memory_write_0_OFFSET           0x700
#define           Output_Buffer_Memory_write_0                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Output_Buffer_Memory_write_0_OFFSET) << 2))

#define             Output_Buffer_Memory_write_0_RD_MASK    0x00000000
#define             Output_Buffer_Memory_write_0_WR_MASK    0xFFFFFFFF
//-------------------------
//Output_Buffer_Memory_write_1
#define           Output_Buffer_Memory_write_1_OFFSET           0x701
#define           Output_Buffer_Memory_write_1                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Output_Buffer_Memory_write_1_OFFSET) << 2))

#define             Output_Buffer_Memory_write_1_RD_MASK    0x00000000
#define             Output_Buffer_Memory_write_1_WR_MASK    0xFFFFFFFF

//-------------------------
//Output_Buffer_Memory_write_79
#define           Output_Buffer_Memory_write_79_OFFSET           0x74f
#define           Output_Buffer_Memory_write_79                        REG32(WCDMA_CS_LB+((WCDMA_ENC_BASE_ADDR+Output_Buffer_Memory_write_79_OFFSET) << 2))

#define             Output_Buffer_Memory_write_79_RD_MASK    0x00000000
#define             Output_Buffer_Memory_write_79_WR_MASK    0xFFFFFFFF

// Function prototype
void WCDMA_EncTestResetValue(void);
void WCDMA_EncTestRegistersAccess(void);

#endif