omap_32_armwdg.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :omap_32_armwdg.h
//
//   Date of Module Modification:4/25/02
//   Date of Generation :5/3/02
//
//
//========================================================================
#include "omap_32_mapping.h"
#ifndef _ARMWDG__H
#define _ARMWDG__H

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define            ARMWDG_CNTL_TIMER_OFFSET                                                                            0x00
#define            ARMWDG_LOAD_TIMER_OFFSET                                                                            0x04
#define            ARMWDG_READ_TIMER_OFFSET                                                                            0x04
#define            ARMWDG_TIMER_MODE_OFFSET                                                                            0x08




//ARMWDG_CNTL_TIMER
//-------------------
#define            ARMWDG_CNTL_TIMER                                                                                   REG32(ARMWDG_BASE_ADDR_ARM+ARMWDG_CNTL_TIMER_OFFSET)


//R/W

#define            ARMWDG_CNTL_TIMER_PTV_POS                                                                             9
#define            ARMWDG_CNTL_TIMER_PTV_NUMB                                                                            3
#define            ARMWDG_CNTL_TIMER_PTV_RES_VAL                                                                         0x0
//R/W

#define            ARMWDG_CNTL_TIMER_AR_POS                                                                              8
#define            ARMWDG_CNTL_TIMER_AR_NUMB                                                                             1
#define            ARMWDG_CNTL_TIMER_AR_RES_VAL                                                                          0x0
//R/W

#define            ARMWDG_CNTL_TIMER_ST_POS                                                                              7
#define            ARMWDG_CNTL_TIMER_ST_NUMB                                                                             1
#define            ARMWDG_CNTL_TIMER_ST_RES_VAL                                                                          0x0
//R/W

//R/W

#define            ARMWDG_CNTL_TIMER_FREE_POS                                                                            1
#define            ARMWDG_CNTL_TIMER_FREE_NUMB                                                                           1
#define            ARMWDG_CNTL_TIMER_FREE_RES_VAL                                                                        0x0
//R/W

//R/W


//ARMWDG_LOAD_TIMER
//-------------------
#define            ARMWDG_LOAD_TIMER                                                                                   REG32(ARMWDG_BASE_ADDR_ARM+ARMWDG_LOAD_TIMER_OFFSET)


//R/W

#define            ARMWDG_LOAD_TIMER_VALUE_TIM_POS                                                                       0
#define            ARMWDG_LOAD_TIMER_VALUE_TIM_NUMB                                                                      16
#define            ARMWDG_LOAD_TIMER_VALUE_TIM_RES_VAL                                                                   0xFFFF
//R


//ARMWDG_READ_TIMER
//-------------------
#define            ARMWDG_READ_TIMER                                                                                   REG32(ARMWDG_BASE_ADDR_ARM+ARMWDG_READ_TIMER_OFFSET)


//R/W

#define            ARMWDG_READ_TIMER_LOAD_TIM_POS                                                                        0
#define            ARMWDG_READ_TIMER_LOAD_TIM_NUMB                                                                       16
#define            ARMWDG_READ_TIMER_LOAD_TIM_RES_VAL                                                                    0xFFFF
//W


//ARMWDG_TIMER_MODE
//-------------------
#define            ARMWDG_TIMER_MODE                                                                                   REG32(ARMWDG_BASE_ADDR_ARM+ARMWDG_TIMER_MODE_OFFSET)


//R/W

#define            ARMWDG_TIMER_MODE_WATCHDOG_POS                                                                        15
#define            ARMWDG_TIMER_MODE_WATCHDOG_NUMB                                                                       1
#define            ARMWDG_TIMER_MODE_WATCHDOG_RES_VAL                                                                    0x1
//R/W

//R/W

#define            ARMWDG_TIMER_MODE_WATCHDOG_DIS_POS                                                                    0
#define            ARMWDG_TIMER_MODE_WATCHDOG_DIS_NUMB                                                                   8
#define            ARMWDG_TIMER_MODE_WATCHDOG_DIS_RES_VAL                                                                0x0
//W

#endif