ocpi.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 2002, (C) Copyright 2002 Texas Instruments.  All rights reserved.

   Filename       	: ocpi.h

   Description    	: Header file for the OCPT1 and OCPT2 module.

   Project        	: OMAP3.2

   Author         	: Pandy Kalimuthu

===============================================================================
*/

#ifndef _OCP__HH
#define _OCP__HH

#include "top.h"
//-------------------------------------------------------------
//                OCP master registers
//-------------------------------------------------------------
#define OCPI_ADDR_FAULT_REG             0xfffec320
#define OCPI_MCMD_FAULT_REG             0xfffec324
#define OCPI_SINT0_REG                  0xfffec328
#define OCPI_ABORT_TYPE_REG             0xfffec32c
#define OCPI_SINT1_REG                  0xfffec330
#define OCPI_PROTECT_REG                0xfffec334
#define OCPI_SECURE_MODE_REG            0xfffec338
#define OCPI_TEST_REG                   0x05000140
#define SECURE_CONTROL_REG              0xFFFED480 

//-------------------------------------------------------------
//                OCP master registers MASK values
//-------------------------------------------------------------
#define OCPI_MCMD_MASK_VALUE            0x00000007
#define OCPI_SINT0_MASK_VALUE           0x00000002
#define OCPI_ABORT_TYPE_MASK_VALUE      0x0000000f
#define OCPI_SINT1_MASK_VALUE           0x00000002
#define OCPI_PROTECT_MASK_VALUE         0x000000ff
#define OCPI_SECURE_MODE_MASK_VALUE     0x0000007f
#define OCPI_TEST_MASK_VALUE            0x0000003f
// LOOP BACK FOR TESTING 
#define OCPI_LOOP_BACK_MASK             0x0ffffffF

//-------------------------------------------------------------
//-- OCPI REGISTERS RESET VALUES
//-------------------------------------------------------------
#define OCPI_ADDR_FAULT_RESET_VALUE     0x00000000
#define OCPI_MCMD_FAULT_RESET_VALUE     0x00000000
#define OCPI_SINT0_RESET_VALUE          0x00000003
#define OCPI_ABORT_TYPE_RESET_VALUE     0x00000000
#define OCPI_SINT1_RESET_VALUE          0x00000003
#define OCPI_PROTECT_RESET_VALUE        0x00000000
#define OCPI_SECURE_MODE_RESET_VALUE    0x0000007f

//-------------------------------------------------------------
//            0CPT1 BASE ADDRESS AND LENGTH 
//-------------------------------------------------------------
//Boot code sitting this place, do not start from 0x20000000 
#define  DBG_OCPT1_1_ADDRESS     0x20000000
// Actually it is 256Mbytes, currently Test bench
// connected to only 64Kbytes
#define  DBG_OCPT1_1_LENGTH      0x00010000

//-------------------------------------------------------------
//            0CPT2 BASE ADDRESS AND LENGTH 
//-------------------------------------------------------------
#define  DBG_OCPT2_1_ADDRESS     0x30000000
// Actually it is 1.2G byte, currently Test bench
// connected to only 1Kbyte
#define  DBG_OCPT2_1_LENGTH      0x00000800

//-------------------------------------------------------------
//            0CPT2 BASE ADDRESS AND LENGTH 
//-------------------------------------------------------------
#define  DBG_OCPT12_1_ADDRESS    0x80000000
#define  DBG_OCPT12_1_LENGTH     0x00001000

//-------------------------------------------------------------
//            0CPT2 BASE ADDRESS AND LENGTH 
//-------------------------------------------------------------
#define  DBG_NON_MAPPED_ADDRESS  0x90000000
#define  DBG_NON_MAPPED_LENGTH   0x50000000

//-------------------------------------------------------------
//                Test REG OCPI VALUES
//-------------------------------------------------------------
#define OCPT1_BASE_ADD_TB_VAL           0x00000022
#define OCPT2_BASE_ADD_TB_VAL           0x00000013
#define OCPT12_BASE_ADD_TB_VAL          0x00000018
#define NON_MAPPED_ADD_TB_VAL           0x00000029
#define EMIFF_BASE_ADD_TB_VAL           0x00000021
#define EMIFS_BASE_ADD_TB_VAL           0x00000020
#define DSP_API_BASE_ADD_TB_VAL         0x0000002e
#define ARM_REHA_BASE_ADD_TB_VAL        0x0000002f

//-------------------------------------------------------------
//             ABORT CMD REG VALUE 
//-------------------------------------------------------------
#define WRITE_CMD_ABORT                0x00000001
#define READ_CMD_ABORT                 0x00000002
#define READEX_CMD_ABORT               0x00000003

//-------------------------------------------------------------
//             ABORT TYPE REG VALUE 
//-------------------------------------------------------------
#define ADD_DEC_ABORT                 0x00000001
#define TRG_ACC_ABORT                 0x00000002
#define PROTECT_ABORT                 0x00000004
#define NON_SUPPORT_MCM_ABORT         0x00000008

//-------------------------------------------------------------
//            PROTECT SET BITS 
//-------------------------------------------------------------
#define SET_EMIFS_AT_PROTECT_MODE     0x00000001
#define SET_EMIFF_AT_PROTECT_MODE     0x00000002
#define SET_OCPT1_AT_PROTECT_MODE     0x00000004
#define SET_OCPT2_AT_PROTECT_MODE     0x00000008
#define SET_OCPT12_AT_PROTECT_MODE    0x00000010
#define SET_RHEAPRI_AT_PROTECT_MODE   0x00000011
#define SET_RHEAPUB_AT_PROTECT_MODE   0x00000012
#define SET_API_AT_PROTECT_MODE       0x00000014

//-------------------------------------------------------------
//            SECURE MODE SET BITS
//-------------------------------------------------------------
#define SET_EMIFS_AT_SECURE_MODE     0x00000001
#define SET_EMIFF_AT_SECURE_MODE     0x00000002
#define SET_OCPT1_AT_SECURE_MODE     0x00000004
#define SET_OCPT2_AT_SECURE_MODE     0x00000008
#define SET_OCPT12_AT_SECURE_MODE    0x00000010
#define SET_RHEAPUB_AT_SECURE_MODE   0x00000011
#define SET_API_AT_SECURE_MODE       0x00000012

//-------------------------------------------------------------
//      OCPTx BASE ADDRESS
//-------------------------------------------------------------
#define OCPI_OCPT1_BASE                 0x20000000 
#define OCPI_OCPT2_BASE                 0x30000000 

//-------------------------------------------------------------
//      DSP API PUBLIC ADDRESS
//-------------------------------------------------------------
// Only following memories are hooked up in the test bench
#define MEM_DSP_STROBE0_CS20_ADD        0xe100a800
#define MEM_DSP_STROBE0_CS21_ADD        0xe100a000
#define MEM_DSP_STROBE1_CS20_ADD        0xe101a800
#define MEM_DSP_STROBE1_CS21_ADD        0xe101a000
#define MEM_DSP_DARAM0_ADD              0xe0000000
#define MEM_DSP_DARAM1_ADD              0xe0002000
#define MEM_DSP_DARAM2_ADD              0xe0004000
#define MEM_DSP_DARAM3_ADD              0xe0006000
#define MEM_DSP_DARAM4_ADD              0xe0008000
#define MEM_DSP_DARAM5_ADD              0xe000a000
#define MEM_DSP_DARAM6_ADD              0xe000c000
#define MEM_DSP_DARAM7_ADD              0xe000e000
#define MEM_DSP_SARAM0_ADD              0xe0010000
#define MEM_DSP_SARAM1_ADD              0xe0012000
#define MEM_DSP_SARAM2_ADD              0xe0014000
#define MEM_DSP_SARAM3_ADD              0xe0016000
#define MEM_DSP_SARAM4_ADD              0xe0018000
#define MEM_DSP_SARAM5_ADD              0xe001a000
#define MEM_DSP_SARAM6_ADD              0xe001c000
#define MEM_DSP_SARAM7_ADD              0xe001e000
#define MEM_DSP_SARAM8_ADD              0xe0020000
#define MEM_DSP_SARAM9_ADD              0xe0022000
#define MEM_DSP_SARAM10_ADD             0xe0024000
#define MEM_DSP_EX_CS0_ADD              0xe0050000
#define MEM_DSP_EX_CS1_ADD              0xe0400000
#define MEM_DSP_EX_CS2_ADD              0xe0800000
#define MEM_DSP_EX_CS3_ADD              0xe0C00000

//-------------------------------------------------------------
//      ERROR_MESSAGES 
//-------------------------------------------------------------
#define DBG_CS0_RAM_6_ERR_MSG           0x2001
#define DBG_CS0_RAM_7_ERR_MSG           0x2002
#define DBG_CS0_RAM_8_ERR_MSG           0x2003
#define DBG_CS0_RAM_9_ERR_MSG           0x2004
#define DBG_CS0_RAM_10_ERR_MSG          0x2005
#define DBG_CS0_RAM_11_ERR_MSG          0x2006
#define DBG_CS1_RAM_5_ERR_MSG           0x2011
#define DBG_CS1_RAM_6_ERR_MSG           0x2012
#define DBG_CS1_RAM_7_ERR_MSG           0x2013
#define DBG_CS1_RAM_8_ERR_MSG           0x2014
#define DBG_CS1_RAM_9_ERR_MSG           0x2015
#define DBG_CS1_RAM_10_ERR_MSG          0x2016
#define DBG_CS2_RAM_3_ERR_MSG           0x2021
#define DBG_CS2_RAM_4_ERR_MSG           0x2022
#define DBG_CS2_RAM_5_ERR_MSG           0x2023
#define DBG_CS2_RAM_6_ERR_MSG           0x2024
#define DBG_CS2_RAM_7_ERR_MSG           0x2025
#define DBG_CS2_RAM_8_ERR_MSG           0x2026
#define DBG_CS3_RAM_3_ERR_MSG           0x2031
#define DBG_CS3_RAM_4_ERR_MSG           0x2032
#define DBG_CS3_RAM_5_ERR_MSG           0x2033
#define DBG_CS3_RAM_6_ERR_MSG           0x2034
#define DBG_CS3_RAM_7_ERR_MSG           0x2035
#define DBG_CS3_RAM_8_ERR_MSG           0x2036
#define DBG_CS4_SDRAM_1_ERR_MSG         0x2041
#define DBG_OCPT1_1_ERR_MSG             0x2110
#define DBG_OCPT2_1_ERR_MSG             0x2120
#define DBG_OCPT12_1_ERR_MSG            0x2130
#define MEM_DSP_RHEA_ERR_MSG            0x2210
#define MEM_DSP_GPIO_ERR_MSG            0x2211
#define MEM_DSP_CLKM_ERR_MSG            0x2212
#define MEM_DSP_DSPMMU_ERR_MSG          0x2213
#define MEM_DSP_MB_ERR_MSG              0x2214
#define MEM_DSP_CS020_ERR_MSG           0x2215
#define MEM_DSP_CS021_ERR_MSG           0x2216
#define MEM_DSP_CS120_ERR_MSG           0x2217
#define MEM_DSP_CS121_ERR_MSG           0x2218
#define MEM_ARM_RHEA_00_ERR_MSG         0x2310
#define MEM_ARM_RHEA_01_ERR_MSG         0x2311
#define MEM_ARM_RHEA_02_ERR_MSG         0x2312
#define MEM_ARM_RHEA_10_ERR_MSG         0x2320
#define MEM_ARM_RHEA_11_ERR_MSG         0x2321
#define MEM_ARM_RHEA_12_ERR_MSG         0x2322
#define MEM_ARM_RHEA_20_ERR_MSG         0x2330
#define MEM_ARM_RHEA_21_ERR_MSG         0x2331
#define MEM_ARM_RHEA_22_ERR_MSG         0x2332
#define MEM_ARM_RHEA_30_ERR_MSG         0x2340
#define MEM_ARM_RHEA_31_ERR_MSG         0x2341
#define MEM_ARM_RHEA_32_ERR_MSG         0x2342
#define OCPI_OCPT1_ERROR                0x2400
#define OCPI_OCPT2_ERROR                0x2401
#define OCPI_OCPT12_ERROR               0x2402
#define OCPI_EMIFF_ERROR                0x2403
#define OCPI_EMIFS_ERROR                0x2404
#define OCPI_REG_RESET_ERROR            0x2405
#define OCPI_REG_RW_ERROR               0x2406
#define OCPI_REG_RONLY_ERROR            0x2407
	
//----------------  END OF OCPI -------------------------------

#endif