📄 pers_conf_a9.h
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#define PERSEUS2_CONF_SECCTRL_CONF_WDA_EN_POS 1
#define PERSEUS2_CONF_SECCTRL_CONF_WDA_EN_NUMB 1
#define PERSEUS2_CONF_SECCTRL_CONF_WDA_EN_RES_VAL 0x1
//R/W1
#define PERSEUS2_CONF_SECCTRL_CONF_WD_ACC_POS 0
#define PERSEUS2_CONF_SECCTRL_CONF_WD_ACC_NUMB 1
#define PERSEUS2_CONF_SECCTRL_CONF_WD_ACC_RES_VAL 0x1
//R/W1
//PERSEUS2_CONF_SPARE1
//-------------------
#define PERSEUS2_CONF_SPARE1 REG32(PERSEUS2_CONF_BASE_ADDR_ARM+PERSEUS2_CONF_SPARE1_OFFSET)
#define PERSEUS2_CONF_SPARE1_SPARE1_POS 0
#define PERSEUS2_CONF_SPARE1_SPARE1_NUMB 32
#define PERSEUS2_CONF_SPARE1_SPARE1_RES_VAL 0x0
//R/W
//PERSEUS2_CONF_SPARE2
//-------------------
#define PERSEUS2_CONF_SPARE2 REG32(PERSEUS2_CONF_BASE_ADDR_ARM+PERSEUS2_CONF_SPARE2_OFFSET)
#define PERSEUS2_CONF_SPARE2_SPARE2_POS 6
#define PERSEUS2_CONF_SPARE2_SPARE2_NUMB 26
#define PERSEUS2_CONF_SPARE2_SPARE2_RES_VAL 0x0
//R/W
#define PERSEUS2_CONF_SPARE2_RNG_IDLE_MODE_POS 5
#define PERSEUS2_CONF_SPARE2_RNG_IDLE_MODE_NUMB 1
#define PERSEUS2_CONF_SPARE2_RNG_IDLE_MODE_RES_VAL 0x1
//R/W
#define PERSEUS2_CONF_SPARE2_PROTECT_CS3_ENABLE_POS 4
#define PERSEUS2_CONF_SPARE2_PROTECT_CS3_ENABLE_NUMB 1
#define PERSEUS2_CONF_SPARE2_PROTECT_CS3_ENABLE_RES_VAL 0x0
//R/W1
#define PERSEUS2_CONF_SPARE2_PROTECT_CS0_ENABLE_POS 3
#define PERSEUS2_CONF_SPARE2_PROTECT_CS0_ENABLE_NUMB 1
#define PERSEUS2_CONF_SPARE2_PROTECT_CS0_ENABLE_RES_VAL 0x0
//R/W1
#define PERSEUS2_CONF_SPARE2_BLOCK_SIZE_POS 1
#define PERSEUS2_CONF_SPARE2_BLOCK_SIZE_NUMB 2
#define PERSEUS2_CONF_SPARE2_BLOCK_SIZE_RES_VAL 0x0
//R/W1
#define PERSEUS2_CONF_SPARE2_P2_IO_CONF0_CONF1_WR_DIS_POS 0
#define PERSEUS2_CONF_SPARE2_P2_IO_CONF0_CONF1_WR_DIS_NUMB 1
#define PERSEUS2_CONF_SPARE2_P2_IO_CONF0_CONF1_WR_DIS_RES_VAL 0x0
//R/W1
//PERSEUS2_CONF_GSM_PBG_IRQ
//-------------------
#define PERSEUS2_CONF_GSM_PBG_IRQ REG32(PERSEUS2_CONF_BASE_ADDR_ARM+PERSEUS2_CONF_GSM_PBG_IRQ_OFFSET)
#define PERSEUS2_CONF_GSM_PBG_IRQ_RESERVED_POS 0
#define PERSEUS2_CONF_GSM_PBG_IRQ_RESERVED_NUMB 16
#define PERSEUS2_CONF_GSM_PBG_IRQ_RESERVED_RES_VAL 0x0
//R/W
//PERSEUS2_CONF_DMA_REQ_CONF
//-------------------
#define PERSEUS2_CONF_DMA_REQ_CONF REG32(PERSEUS2_CONF_BASE_ADDR_ARM+PERSEUS2_CONF_DMA_REQ_CONF_OFFSET)
#define PERSEUS2_CONF_DMA_REQ_CONF_RESERVED_POS 31
#define PERSEUS2_CONF_DMA_REQ_CONF_RESERVED_NUMB 1
#define PERSEUS2_CONF_DMA_REQ_CONF_RESERVED_RES_VAL 0x0
//R/W
#define PERSEUS2_CONF_DMA_REQ_CONF_DMA_EDGE_EN_POS 0
#define PERSEUS2_CONF_DMA_REQ_CONF_DMA_EDGE_EN_NUMB 31
#define PERSEUS2_CONF_DMA_REQ_CONF_DMA_EDGE_EN_RES_VAL 0x7FFFFFFF
//R/W
//PERSEUS2_CONF_PE_CONF_NO_DUAL
//-------------------
#define PERSEUS2_CONF_PE_CONF_NO_DUAL REG32(PERSEUS2_CONF_BASE_ADDR_ARM+PERSEUS2_CONF_PE_CONF_NO_DUAL_OFFSET)
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_RESERVED_POS 8
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_RESERVED_NUMB 24
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_RESERVED_RES_VAL 0X0
//R/W
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_ON_NOFF_POS 7
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_ON_NOFF_NUMB 1
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_ON_NOFF_RES_VAL 0x0
//R/W
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_MPU_NRST_POS 6
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_MPU_NRST_NUMB 1
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_MPU_NRST_RES_VAL 0x1
//R/W
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_NRESPWRON_POS 5
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_NRESPWRON_NUMB 1
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_NRESPWRON_RES_VAL 0x1
//R/W
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_NBSCAN_POS 4
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_NBSCAN_NUMB 1
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_NBSCAN_RES_VAL 0x1
//R/W
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_TDI_POS 3
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_TDI_NUMB 1
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_TDI_RES_VAL 0x1
//R/W
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_TCK_POS 2
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_TCK_NUMB 1
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_TCK_RES_VAL 0x1
//R/W
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_NTRST_POS 1
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_NTRST_NUMB 1
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_NTRST_RES_VAL 0x1
//R/W
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_TMS_POS 0
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_TMS_NUMB 1
#define PERSEUS2_CONF_PE_CONF_NO_DUAL_PE_TMS_RES_VAL 0x1
//R/W
//PERSEUS25_CONF_PERSEUS2_IO_CONF0
//-------------------
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0 REG32(PERSEUS25_CONF_BASE_ADDR_ARM+PERSEUS25_CONF_PERSEUS2_IO_CONF0_OFFSET)
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPEN1_POS 29
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPEN1_NUMB 3
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPEN1_RES_VAL 0x6
//R/W
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_PE_TPU_TSPEN1_POS 28
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_PE_TPU_TSPEN1_NUMB 1
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_PE_TPU_TSPEN1_RES_VAL 0x1
//R/W
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPEN0_POS 25
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPEN0_NUMB 3
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPEN0_RES_VAL 0x6
//R/W
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_PE_TPU_TSPEN0_POS 24
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_PE_TPU_TSPEN0_NUMB 1
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_PE_TPU_TSPEN0_RES_VAL 0x1
//R/W
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPACT4_POS 21
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPACT4_NUMB 3
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPACT4_RES_VAL 0x6
//R/W
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_PE_TPU_TSPACT4_POS 20
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_PE_TPU_TSPACT4_NUMB 1
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_PE_TPU_TSPACT4_RES_VAL 0x1
//R/W
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPACT3_POS 17
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPACT3_NUMB 3
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_D_TPU_TSPACT3_RES_VAL 0x6
//R/W
#define PERSEUS25_CONF_PERSEUS2_IO_CONF0_PE_TPU_TSPACT3_POS ⌨️ 快捷键说明
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