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📄 system-macros.h.s

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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	WRITE_CONTROL_REG $register
	MEND

	MACRO
$label	ICACHE_ON $register
$label		
	READ_CONTROL_REG $register
	ORR	$register, $register, #I_bit
	WRITE_CONTROL_REG $register
	MEND

	MACRO
$label	PU_ON $register
$label
	READ_CONTROL_REG $register
	ORR	$register, $register, #M_bit
	WRITE_CONTROL_REG $register
	MEND

	MACRO
$label	WB_ON $register
$label
	READ_CONTROL_REG $register
	ORR	$register, $register, #W_bit
	WRITE_CONTROL_REG $register
	MEND

	MACRO
$label	DCACHE_OFF $register
$label
	READ_CONTROL_REG $register
	BIC	$register, $register, #C_bit
	WRITE_CONTROL_REG $register
	MEND

	MACRO
$label	ICACHE_OFF $register
$label
	READ_CONTROL_REG $register
	BIC	$register, $register, #I_bit
	WRITE_CONTROL_REG $register
	MEND

	MACRO
$label	PU_OFF $register
$label
	READ_CONTROL_REG $register
	BIC	$register, $register, #M_bit
	WRITE_CONTROL_REG $register
	MEND

	MACRO
$label	WB_OFF $register
$label
	READ_CONTROL_REG $register
	BIC	$register, $register, #W_bit
	WRITE_CONTROL_REG $register
	MEND

	MACRO
$label	SET_HIVECS $register
$label
	; [ ?? /= "WinCE" !, 1, "Only supported for WinCE extensions
	READ_CONTROL_REG $register
	ORR	$register, $register, #V_bit
	WRITE_CONTROL_REG $register
HIGH_VECTORS SETL {TRUE}
	MEND

	MACRO
$label	RESET_HIVECS $register
$label
	; [ ?? /= "WinCE" !, 1, "Only supported for WinCE extensions
	READ_CONTROL_REG $register
	BIC	$register, $register, #V_bit
	WRITE_CONTROL_REG $register
HIGH_VECTORS SETL {FALSE}
	MEND


;*******************************************************************************
;		Register2:   Translation Table Base/Cacheable register
;*******************************************************************************
		
;------------------------------------------------------------------------------
; read, write pointer to translation table base register
; Supports both Arch 3 & Arch 4 processors
;------------------------------------------------------------------------------

 MACRO
	READ_TTBR $register

	ReadCoprocReg	2, $register

 MEND

 MACRO
	WRITE_TTBR $register
	FLUSH_PU_FIFO
	WriteCoprocReg	2, $register
 MEND

;------------------------------------------------------------------------------
; Macro:	[label] WRITE_ICACHEABLE $register
;
; Function:	THis macro writes the Instuction Cacheable bits in register2.
;		$register - contains the 8 bit value for the I cacheable bits
; 		right aligned. .ie the macro will shift into correct postion
; 		for register 2.
;		
; Internally:	
;


		MACRO
$label		WRITE_ICACHEABLE $register
		LOCAL
$label		B	jump$l
store$l		%	8				; temporary storage for r0,r1
jump$l		STR	r0, store$l			; save r0
		STR	r1, store$l+4			; save r1
		MOV	r1, $register			; incase $register is r0!
		ReadCoprocReg	2, r0, 1
		BIC	r0, r0, #0xFF			; clear the Icache bits
		ORR	r0, r0, r1			; OR in new Icache bits
		WriteCoprocReg	2, r0, 1
		LDR	r0, store$l			; restore r0
		LDR	r1, store$l+4			; restore r1
		LOCAL_END
		MEND

;------------------------------------------------------------------------------
; Macro:	[label] READ_ICACHEABLE $register
;
; Function:	THis macro reads the Instuction Cacheable bits in register2.
;		$register - returns the 8 bit value for the I cacheable bits
; 		right aligned.
;		
; Internally:	
;


		MACRO
$label		READ_ICACHEABLE $register
$label
		ReadCoprocReg	2, $register, 1		; read the cacheable register
		MEND

;------------------------------------------------------------------------------
; Macro:	[label] WRITE_DCACHEABLE $register
;
; Function:	THis macro writes the Data Cacheable bits in register2.
;		$register - contains the 8 bit value for the D cacheable bits.
;		
; Internally:	
;


		MACRO
$label		WRITE_DCACHEABLE $register
		LOCAL
$label		B	jump$l
store$l		%	8				; temporary storage for r0,r1
jump$l		STR	r0, store$l			; save r0
		STR	r1, store$l+4			; save r1
		MOV	r1, $register			; incase $register is r0!
		ReadCoprocReg	2, r0
		BIC	r0, r0, #0xFF			; clear the Dcache bits
		ORR	r0, r0, r1			; OR in new Dcache bits
		WriteCoprocReg	2, r0			; write to register2
		LDR	r0, store$l			; restore r0
		LDR	r1, store$l+4			; restore r1
		LOCAL_END
		MEND
		
;------------------------------------------------------------------------------
; Macro:	[label] READ_DCACHEABLE $register
;
; Function:	This macro reads the Data Cacheable bits in register2.
;		$register - returns the 8 bit value for the D cacheable bits.
;		
; Internally:	
;


		MACRO
$label		READ_DCACHEABLE $register
$label
		ReadCoprocReg	2, $register	; read the cacheable register
		MEND

;*******************************************************************************
;		Register3:   Domain Access Control/ WB Control register
;*******************************************************************************
		
;------------------------------------------------------------------------------
; read, write domain register; Supports both Arch 3 & Arch 4 processors
;------------------------------------------------------------------------------

 MACRO
	READ_DOMAIN_REG $register

	ReadCoprocReg	3, $register
 MEND

 MACRO
	WRITE_DOMAIN_REG $register
	WriteCoprocReg	3, $register
 MEND

;------------------------------------------------------------------------------
; Macro:	[label] WRITE_BUFFERABLE $register
;
; Function:	THis macro writes the Write Buffer Control Bits in register3.
;		$register - contains 8 bit value for control bits to be written
;		
;
; Internally:	
;


		MACRO
$label		WRITE_BUFFERABLE $register
$label
		WriteCoprocReg	3, $register
		MEND

;------------------------------------------------------------------------------
; Macro:	[label] READ_BUFFERABLE $register
;
; Function:	THis macro reads the Write Buffer Control Bits in register3.
;		$register - 8 bit value for control bits returned in $register.
;		
;
; Internally:	
;


		MACRO
$label		READ_BUFFERABLE $register
$label
		ReadCoprocReg	3, $register
		MEND

;*******************************************************************************
;		Register5:   Fault Status/ Protection registers
;*******************************************************************************
		
;------------------------------------------------------------------------------
; Macro:	[label] WRITE_IAP $register
;
; Function:	THis macro write the Instruction Access Protection bits in
;		the Instruction Space Protection Register.
;		$register - contains the 16 IAP bits to be written.		
;
; Internally:	
;

		MACRO
$label		WRITE_IAP $register
$label
		MCR	p15, 0, $register, c5, c0, 1
		MEND

;------------------------------------------------------------------------------
; Macro:	[label] READ_IAP $register
;
; Function:	THis macro reads the Instruction Access Protection bits in
;		the Instruction Space Protection Register.
;		$register - returns the 16 IAP bits to be written.		
;
; Internally:	
;

		MACRO
$label		READ_IAP $register
$label
		MRC	p15, 0, $register, c5, c0, 1
		MEND

;------------------------------------------------------------------------------
; Macro:        IAP_GET $register
;
; Function:     This macro reads the Instruction Access Permission bits in the
;               Instruction Space Protection Register.
;               $register - returns the 32 IAP bits to be read.

	MACRO	
	IAP_GET $register
	MRC     p15, 0, $register, c5, c0, 3
	MEND
	
;------------------------------------------------------------------------------
; Macro:        IAP_PUT $register
;
; Function:     This macro writess the Instruction Access Permission bits in the
;               Instruction Space Protection Register.
;               $register - returns the 32 IAP bits to be written.

	MACRO	
	IAP_PUT $register
	MCR     p15, 0, $register, c5, c0, 3
	MEND

;------------------------------------------------------------------------------
; Macro:	[label] WRITE_DAP $register
;
; Function:	THis macro write the Data Access Protection bits in
;		the Data Space Protection Register.
;		$register - contains the 16 IAP bits to be written.		
;
; Internally:	
;

		MACRO
$label		WRITE_DAP $register
$label
		MCR	p15, 0, $register, c5, c0, 0
		MEND

;------------------------------------------------------------------------------
; Macro:	[label] READ_DAP $register
;
; Function:	THis macro reads the Data Access Protection bits in
;		the Data Space Protection Register.
;		$register - returns the 16 IAP bits to be written.		
;
; Internally:	
;

		MACRO
$label		READ_DAP $register
$label
		MRC	p15, 0, $register, c5, c0, 0
		MEND

;------------------------------------------------------------------------------
; Macro:        DAP_GET $register
;
; Function:     This macro reads the Data Access Permission bits in the
;               Data Space Protection Register.
;               $register - returns the 32 DAP bits to be read.

	MACRO	
	DAP_GET $register
	MRC     p15, 0, $register, c5, c0, 2
	MEND
	
;------------------------------------------------------------------------------
; Macro:        DAP_PUT $register
;
; Function:     This macro writess the Data Access Permission bits in the
;               Data Space Protection Register.
;               $register - returns the 32 DAP bits to be written.

	MACRO	
	DAP_PUT $register
	MCR     p15, 0, $register, c5, c0, 2
	MEND

 MACRO		;; this is Kami's version for ARM810 !!??!!
	READ_FSR $register	
	MRC	p15, 0, $register, c5, c0, 0
	AND	$register, $register, #&F
 MEND

 MACRO		;; this one works with the arch_mem AVS
	READ_FSReg $register
	MRC	p15, 0, $register, c5, c0, 0
	
	[ "$PROC" /= "SA2"
	AND	$register, $register, #&FF

	|
	LOCAL
	B	jump$l
store$l	%	4		   ; temporary storage for R3
jump$l	STR	R3, store$l        ; save current R3 value
	MOV 	R3, #&700
	ORR 	R3, R3, #&FF
	AND 	$register, $register, R3         ; mask invalid bits
	LDR 	R3, store$l        ; return R3 to its original value
	LOCAL_END
	]
 MEND

 MACRO
	READ_DOMAIN $register
	MRC	p15, 0, $register, c5, c0, 0
	AND	$register, $register, #&F0
	MOV	$register, $register, LSR #4
 MEND

 MACRO
	WRITE_FSR $register
	AND	$register, $register, #&FF
	MCR	p15, 0, $register, c5, c0, 0
 MEND

;*******************************************************************************
;		Register6:   Fault Address/ Protection Region base/size register
;*******************************************************************************

;------------------------------------------------------------------------------
; Macro:	[label] WRITE_DREGION_BASE_REG $basereg, $basevalue
;
; Function:	Writes to the Protection Unit Region Base Address/ Size register.
;
; Internally:	$basereg is the base register number (c0->c7).
; 		$basevalue contains the base register data in the format:-
; 		(31->12) base offset, (11->6) SBZ, (5->1) size, (0) enable.
;

		MACRO
$label		WRITE_DREGION_BASE_REG $basereg, $basevalue
$label
		MCR	p15, 0, $basevalue, c6, $basereg, 0 ; write base/size reg
		MEND
		
;------------------------------------------------------------------------------
; Macro:	[label] READ_DREGION_BASE_REG $basereg, $basevalue
;
; Function:	Reads the Protection Unit Region Base Address/ Size register.
;
; Internally:	$basereg contains the base register number (0->15).
;		$basevalue returns the base register data in the format:-
; 		(31->12) base offset, (11->6) SBZ, (5->1) size, (0) enable.

		MACRO
$label		READ_DREGION_BASE_REG $basereg, $basevalue
$label
		MRC	p15, 0, $basevalue, c6, $basereg, 0 ; write base/size reg
		MEND
		
;------------------------------------------------------------------------------
; Macro:	[label] WRITE_IREGION_BASE_REG $basereg, $basevalue
;
; Function:	Writes to the Protection Unit Region Base Address/ Size register.
;
; Internally:	$basereg is the base register number (c0->c7).
; 		$basevalue contains the base register data in the format:-
; 		(31->12) base offset, (11->6) SBZ, (5->1) size, (0) enable.
;

		MACRO
$label		WRITE_IREGION_BASE_REG $basereg, $basevalue
$label
		MCR	p15, 0, $basevalue, c6, $basereg, 1 ; write base/size reg
		MEND
		
;------------------------------------------------------------------------------
; Macro:	[label] READ_IREGION_BASE_REG $basereg, $basevalue
;
; Function:	Reads the Protection Unit Region Base Address/ Size register.
;
; Internally:	$basereg contains the base register number (0->15).
;		$basevalue returns the base register data in the format:-
; 		(31->12) base offset, (11->6) SBZ, (5->1) size, (0) enable.

		MACRO
$label		READ_IREGION_BASE_REG $basereg, $basevalue
$label
		MRC	p15, 0, $basevalue, c6, $basereg, 1 ; write base/size reg
		MEND
		
;------------------------------------------------------------------------------
; read, write Fault Address Register (FAR)
;------------------------------------------------------------------------------

 MACRO
	READ_FAR $register
	MRC	p15, 0, $register, c6, c0, 0
 MEND
 
 MACRO
	WRITE_FAR $register
	MCR	p15, 0, $register, c6, c0, 0
 MEND

;*******************************************************************************
;		Register7:   Cache Functions register
;*******************************************************************************
		
;------------------------------------------------------------------------------
; Macro:	[label] FLUSH_CACHE <register>
;
12345

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