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📄 system-macros.h.s

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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;
; Macro:	$label READ_ICACHE_NSEGMENTS $reg
;
; Function:	Reads number of segments in ICache into R$reg.
;
; Internally:	All other registers preserved.
;

	MACRO
$label	READ_ICACHE_NSEGMENTS $reg
$label
		
	[ "$reg" ="R0" :LOR: "$reg" ="r0" :LOR: "$reg" ="R1" :LOR: "$reg" ="r1" :LOR: "$reg" ="R2" :LOR: "$reg" ="r2"
	! 1,"\nNumber of ICache segments cannot be read into R0, R1, or R2"
	]
		
	PRESERVE 0, 2
	
	MRC	p15, 0, r0, c0, c0, 1			; Read cache type register
	AND	r1, r0, #2_11				; bits[1:0]
	AND	r2, r0, #2_111000			; bits[5:3] LSL #3
	[ SEGMENT_ASSOCIATIVE
	MOV	r1, r2, LSR #3				; bits[5:3]
	MOV	r2, #1
	MOV	$reg, r2, LSL r1			; 2 ^ bits[5:3]
	|
	ADD	r1, r1, r2, LSR #3			; bits[5:3] + bits[1:0]
	AND	r2, r0, #2_111000000			; bits[8:6] LSL #6
	SUB	r1, r1, r2, LSR #6			; bits[5:3] + bits[1:0] - bits[8:6]
	RSB	r1, r1, #6				; bits[8:6] - bits[5:3] - bits[1:0] + 6
	MOV	r2, #1
	MOV	$reg, r2, LSL r1			; 2 ^ (bits[8:6] - bits[5:3] - bits[1:0] + 6)
	]
	
	RESTORE 0, 2
	MEND

;------------------------------------------------------------------------------
;
; Macro:	$label READ_DCACHE_NSEGMENTS $reg
;
; Function:	Reads number of segments in DCache into R$reg.
;
; Internally:	All other registers preserved.
;

	MACRO
$label	READ_DCACHE_NSEGMENTS $reg
$label
		
	[ "$reg" ="R0" :LOR: "$reg" ="r0" :LOR: "$reg" ="R1" :LOR: "$reg" ="r1" :LOR: "$reg" ="R2" :LOR: "$reg" ="r2"
	! 1,"\nNumber of DCache segments cannot be read into R0, R1, or R2"
	]
		
	PRESERVE 0, 2
	
	MRC	p15, 0, r0, c0, c0, 1			; Read cache type register
	MOV	r0, r0, LSR #12				; Shift to make subsequent code identical to ICache
	AND	r1, r0, #2_11				; bits[1:0]
	AND	r2, r0, #2_111000			; bits[5:3] LSL #3
	[ SEGMENT_ASSOCIATIVE
	MOV	r1, r2, LSR #3				; bits[5:3]
	MOV	r2, #1
	MOV	$reg, r2, LSL r1			; 2 ^ bits[5:3]
	|
	ADD	r1, r1, r2, LSR #3			; bits[5:3] + bits[1:0]
	AND	r2, r0, #2_111000000			; bits[8:6] LSL #6
	SUB	r1, r1, r2, LSR #6			; bits[5:3] + bits[1:0] - bits[8:6]
	RSB	r1, r1, #6				; bits[8:6] - bits[5:3] - bits[1:0] + 6
	MOV	r2, #1
	MOV	$reg, r2, LSL r1			; 2 ^ (bits[8:6] - bits[5:3] - bits[1:0] + 6)
	]
	
	RESTORE 0, 2
	MEND

	
;------------------------------------------------------------------------------
;
; Macro:	$label READ_DCACHE_SIZE $reg
;
; Function:	Reads DCache Size into R$reg.
;
; Internally:	All other registers preserved.
;

	MACRO
$label	READ_DCACHE_SIZE $reg
$label	LOCAL
		
	[ "$reg" ="R0" :LOR: "$reg" ="r0" 
	! 1,"\nDCache size cannot be read into R0"
	]
		
	PRESERVE 0, 0
	
	MRC	p15, 0, r0, c0, c0, 1			; Read cache type register
	MOV	r0, r0, LSR #12				; Shift to make subsequent code identical to ICache
	AND	$reg, r0, #2_1111000000			; bits[9:6]
	
	RESTORE 0, 0
	LOCAL_END
	MEND

;------------------------------------------------------------------------------
;
; Macro:	$label READ_ICACHE_SIZE $reg
;
; Function:	Reads ICache Size into R$reg.
;
; Internally:	All other registers preserved.
;

	MACRO
$label	READ_ICACHE_SIZE $reg
$label	LOCAL
		
	[ "$reg" ="R0" :LOR: "$reg" ="r0" 
	! 1,"\nICache size cannot be read into R0"
	]
		
	PRESERVE 0, 0
	
	MRC	p15, 0, r0, c0, c0, 1			; Read cache type register
	AND	$reg, r0, #2_1111000000			; bits[9:6]
	
	RESTORE 0, 0
	LOCAL_END
	MEND

	
;*******************************************************************************
;		Register1:  Control register
;*******************************************************************************
		
;------------------------------------------------------------------------------
; read, set and reseting of control flags in register 1
;------------------------------------------------------------------------------
;
;

;; Constants used to identify bits in the CP15 Reg1 Control Reg

M_bit	*	0x1	; Enable Address translation & page access
A_bit	*	0x2	; Alignment fault enable/disable
C_bit	*	0x4	; Unified/Data cache enable/disable
W_bit	*	0x8	; Write buffer enable/disable
P_bit	*	0x10	; Used to control the Prog32 signal in some cores
D_bit	*	0x20	; Used to control the Data32 signal in some cores
L_bit	*	0x40	; Implementation dependant (configures LateAbort Sign)
B_bit	*	0x80	; Big(1)/Little(0) Endian configuration
S_bit	*	0x100	; System protection bit
R_bit	*	0x200	; ROM protection bit
F_bit	*	0x400	; Implementation dependent (controls CoProc clk freq)
Z_bit	*	0x800	; Implementation dependent (turn on branch prediction)
I_bit	*	0x1000	; ICache enable/disable in Harvard designs
V_bit	*	0x2000	; Alternate Vectors select bit (WinCE extentions)
ME_bit  *       0x800000        ; Mixed(1)/Fixed(0) Endian configuration
U_Bit  *       0x00400000        ; Mixed(1)/Fixed(0) Endian configuration

;------------------------------------------------------------------------------
; Macro:	[label] READ_CONTROL_REG <register>
;
; Function:	Reads CP15 register1 and return result in supplied register.
;
; Internally:	$register used as destination register.
;

	MACRO
$label	READ_CONTROL_REG $register
	ReadCoprocReg	1, $register
 	MEND


 MACRO
	WRITE_CONTROL_REG $register
	WriteCoprocReg	1, $register
 MEND

;; MMU bit Access

 MACRO
	READ_MMU_BIT $register

	READ_CONTROL_REG $register
	AND	$register, $register,#M_bit
 MEND

 MACRO
	MMU_ON $register

	READ_CONTROL_REG $register
	ORR	$register, $register,#M_bit
	WRITE_CONTROL_REG $register
 MEND

 MACRO	
	MMU_OFF $register

	WBUFFER_OFF	$register
	CACHE_OFF	$register
	READ_CONTROL_REG $register
	BIC	$register, $register, #M_bit
	WRITE_CONTROL_REG $register
	FLUSH_PU_FIFO
 MEND

 ; only switch off the mmu
 MACRO	
	MMU_OFF_ONLY $register

	READ_CONTROL_REG $register
	BIC	$register, $register, #M_bit
	WRITE_CONTROL_REG $register
 MEND

; read, set, reset Alignment_Fault_Bit
 MACRO
	READ_ALIGNMENT_BIT $register

	READ_CONTROL_REG $register
	MOV	$register, $register, LSR #1
	AND	$register, $register, #1
 MEND

 MACRO
	SET_ALIGNMENT_BIT $register
	READ_CONTROL_REG $register
	ORR	$register, $register, #A_bit
	WRITE_CONTROL_REG $register
 MEND

 MACRO	
	RESET_ALIGNMENT_BIT $register
	READ_CONTROL_REG $register
	BIC	$register, $register, #A_bit
	WRITE_CONTROL_REG $register
 MEND

; read, set, reset Cache_Bit
 MACRO
	READ_CACHE_BIT $register

	READ_CONTROL_REG $register
	MOV	$register, $register, LSR #2
	AND	$register, $register, #1
 MEND

  MACRO
	CACHE_ON $register

	READ_CONTROL_REG $register
	ORR	$register, $register, #C_bit

	IF HARVARD
	ORR	$register, $register, #I_bit
	ENDIF

	WRITE_CONTROL_REG $register
  MEND

  MACRO	
	CACHE_OFF $register

	READ_CONTROL_REG $register
	BIC	$register, $register, #C_bit

	IF HARVARD
	BIC	$register, $register, #I_bit
	ENDIF

	WRITE_CONTROL_REG $register
  MEND


; read, set, reset Write_Buffer_Bit
 MACRO
	READ_WBUFFER_BIT $register

	READ_CONTROL_REG $register
	MOV	$register, $register, LSR #3
	AND	$register, $register, #1
 MEND

 MACRO
	WBUFFER_ON $register

	READ_CONTROL_REG $register
        [ SEGMENT_ASSOCIATIVE
	ORR	$register, $register, #M_bit
	|
	ORR	$register, $register, #W_bit
	]
	WRITE_CONTROL_REG $register
 MEND

 MACRO	
	WBUFFER_OFF $register
	READ_CONTROL_REG $register
        [ SEGMENT_ASSOCIATIVE
	BIC	$register, $register, #M_bit
	|
	BIC	$register, $register, #W_bit
	]
	WRITE_CONTROL_REG $register
 MEND

; read, P_Bit
 MACRO
	READ_P_BIT $register
	READ_CONTROL_REG $register
	MOV	$register, $register, LSR #4
	AND	$register, $register, #1
 MEND

; read, D_Bit
 MACRO
	READ_D_BIT $register
	READ_CONTROL_REG $register
	MOV	$register, $register, LSR #5
	AND	$register, $register, #1
 MEND

; read, L_Bit
 MACRO
	READ_L_BIT $register
	READ_CONTROL_REG $register
	MOV	$register, $register, LSR #6
	AND	$register, $register, #1
 MEND

; read, set, reset Endian_Bit
 MACRO
	READ_ENDIAN_BIT $register

	READ_CONTROL_REG $register
	MOV	$register, $register, LSR #7
	AND	$register, $register, #1
 MEND

 MACRO
	SET_BIG_ENDIAN $register

	READ_CONTROL_REG $register
	ORR	$register, $register, #B_bit

	IF 	"$PROC" = "SARMsd"
	BIC	$register,$register,#0xFF000000
	BIC	$register,$register,#0xFF0000
	BIC	$register,$register,#0xE000
	ENDIF

	WRITE_CONTROL_REG $register
 MEND

 MACRO	
	SET_LITTLE_ENDIAN $register
	READ_CONTROL_REG $register
	BIC	$register, $register, #B_bit
	WRITE_CONTROL_REG $register
 MEND

; read, set, reset Mixed_Endian_Bit
 MACRO
        READ_MIXED_ENDIAN_BIT $register

        READ_CONTROL_REG $register
        MOV     $register, $register, LSR #23
        AND     $register, $register, #1
 MEND

 MACRO
        SET_MIXED_ENDIAN $register

        READ_CONTROL_REG $register
        ORR     $register, $register, #U_Bit
        WRITE_CONTROL_REG $register
 MEND

 MACRO
        SET_FIXED_ENDIAN $register
        READ_CONTROL_REG $register
        BIC     $register, $register, #U_Bit
        WRITE_CONTROL_REG $register
 MEND

; read, set, reset S_Bit
 MACRO
	READ_S_BIT $register
	READ_CONTROL_REG $register
	MOV	$register, $register, LSR #8
	AND	$register, $register, #1
 MEND

 MACRO
	SET_S_BIT $register

	READ_CONTROL_REG $register
	ORR	$register, $register, #S_bit
	WRITE_CONTROL_REG $register
 MEND

 MACRO
	RESET_S_BIT $register

	READ_CONTROL_REG $register
	BIC	$register, $register, #S_bit
	WRITE_CONTROL_REG $register
 MEND

; read, set, reset R_BIT
 MACRO
	READ_R_BIT $register

	READ_CONTROL_REG $register
	MOV	$register, $register, LSR #9
	AND	$register, $register, #1
 MEND

 MACRO
	SET_R_BIT $register
	READ_CONTROL_REG $register
	ORR	$register, $register, #R_bit
	WRITE_CONTROL_REG $register
 MEND

 MACRO	
	RESET_R_BIT $register
	READ_CONTROL_REG $register
	BIC	$register, $register, #R_bit
	WRITE_CONTROL_REG $register
 MEND

; read, F_BIT
 MACRO
	READ_F_BIT $register

	READ_CONTROL_REG $register
	MOV	$register, $register, LSR #10
	AND	$register, $register, #1
 MEND

; read, set, reset Branch_Prediction_Bit
 MACRO
	READ_BP_BIT $register
	IF "$PROC" /= "ARM8" :LAND: "$PROC" /= "ARM810"
	!	1,"Branch prediction only supported on ARM8/ARM810"
	ELSE
	MRC	p15, 0, $register, c1, c0, 0
	MOV	$register, $register, LSR #11
	AND	$register, $register, #1
	ENDIF
 MEND

 MACRO
	BP_ON $register
	READ_BP_BIT $register
	IF "$PROC" /= "ARM8" :LAND: "$PROC" /= "ARM810"
	!	1,"Branch prediction only supported on ARM8/ARM810"
	ELSE
	MRC	p15, 0, $register, c1, c0, 0
	ORR	$register, $register, #Z_bit
	MCR	p15, 0, $register, c1, c0, 0
	FLUSH_PU_FIFO
	ENDIF
 MEND

; see 810 cache documantation for details of following routine
 MACRO	
$lab	BP_OFF $register
	IF "$PROC" /= "ARM8" :LAND: "$PROC" /= "ARM810"
	!	1,"Branch prediction only supported on ARM8/ARM810"
	ELSE

$lab	MRC	p15, 0, $register, c1, c0, 0
	BIC	$register, $register, #Z_bit
	MCR	p15, 0, $register, c1, c0, 0
	FLUSH_PU_FIFO
	ENDIF
 MEND

	MACRO
$label	DCACHE_ON $register
$label
	READ_CONTROL_REG $register
	ORR	$register, $register, #C_bit
12345

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