📄 system-macros.h.s
字号:
;*******************************************************************************
;*
;* The confidential and proprietary information contained in this file may
;* only be used by a person authorised under and to the extent permitted
;* by a subsisting licensing agreement from ARM Limited.
;*
;* (C) COPYRIGHT 1996-1999 ARM Limited.
;* ALL RIGHTS RESERVED
;*
;* This entire notice must be reproduced on all copies of this file
;* and copies of this file may only be made by a person if such person is
;* permitted to do so under the terms of a subsisting license agreement
;* from ARM Limited.
;*
;* Validation Suite Macros and Definitions
;* =======================================
;*
;* Origin: ARM9 Validation Suite
;* Author: Bryan Dickman 13/12/96
;* $Author: pmarchay $
;* $Revision: 1.34 $
;* $Date: Wed Sep 12 10:46:45 2001 $
;*
;*******************************************************************************
;Prevent System-Macros being included twice
[ :DEF: Got_System_Macros
! 0, "\n\tWARNING: System-Macros already included."
|
GBLL Got_System_Macros
;turn off normal listing for include files
;OPT 2
;*******************************************************************************
;*
;* Description: This INCLUDE file contains the set of "system" macros required
;* by the validation test programs to control the functional logic
;* blocks that interface to the core directly .ie Caches, MMUs,
;* TLBs, Write Buffers etc... These units are all controlled via
;* the CP15 coprocessor.
;*
;* [*] denotes macros which have been superseded, typically
;* by the macro(s) immediately after them.
;*
;* Contents: CP15 Register Access MACROs
;* L1Section
;* L1Page
;* L1TinyPage
;* L2SmallPage
;* L2LargePage
;* L2TinyPage
;* FLUSH_PU_FIFO
;* System_Init
;*
;* CP15 Register0: ID register
;*
;* READ_ID_REG
;* READ_ICACHE_NSEGMENTS
;* READ_DCACHE_NSEGMENTS
;*
;* CP15 Register1: Control register
;*
;* READ_CONTROL_REG
;* WRITE_CONTROL_REG
;* READ_MMU_BIT
;* MMU_ON
;* MMU_OFF
;* MMU_OFF_ONLY
;* READ_ALIGNMENT_BIT
;* SET_ALIGNMENT_BIT
;* READ_CACHE_BIT
;* CACHE_OFF
;* CACHE_ON
;* READ_WBUFFER_BIT
;* WBUFFER_ON
;* WBUFFER_OFF
;* READ_P_BIT
;* READ_D_BIT
;* READ_L_BIT
;* READ_ENDIAN_BIT
;* SET_BIG_ENDIAN
;* SET_LITTLE_ENDIAN
;* READ_MIXED_ENDIAN_BIT
;* SET_MIXED_ENDIAN
;* SET_FIXED_ENDIAN
;* READ_S_BIT
;* SET_S_BIT
;* RESET_S_BIT
;* SET_R_BIT
;* RESET_R_BIT
;* READ_F_BIT
;* READ_BP_BIT
;* BP_ON
;* BP_OFF
;* DCACHE_ON
;* ICACHE_ON
;* PU_ON
;* WB_ON
;* DCACHE_OFF
;* ICACHE_OFF
;* PU_OFF
;* WB_OFF
;*
;* CP15 Register2: Translation Table Base Register/
;* Cacheable register
;*
;* READ_TTBR
;* WRITE_TTBR
;* WRITE_ICACHEABLE
;* READ_ICACHEABLE
;* WRITE_DCACHEABLE
;* READ_DCACHEABLE
;*
;* CP15 Register3: Domain Access Control Register/
;* Write Buffer Control
;*
;* READ_DOMAIN_REG
;* WRITE_DOMAIN_REG
;* WRITE_BUFFERABLE
;* READ_BUFFERABLE
;*
;* CP15 Register4: Instruction Space Protection
;*
;* WRITE_IAP [*] (Compatibility mode)
;* IAP_PUT
;* READ_IAP [*] (Compatibility mode)
;* IAP_GET
;*
;* CP15 Register5: Fault Status Register/
;* Data Space Protection
;*
;* WRITE_DAP [*] (Compatibility mode)
;* DAP_PUT
;* READ_DAP [*] (Compatibility mode)
;* DAP_GET
;* READ_FSR
;* READ_FSReg
;* READ_DOMAIN
;* WRITE_FSR
;*
;* CP15 Register6: Fault Address Register/
;* Protection Region Base/Size Control
;*
;* WRITE_REGION_BASE_REG
;* READ_REGION_BASE_REG
;* READ_FAR
;* WRITE_FAR
;*
;* CP15 Register7: Cache Functions
;*
;* FLUSH_CACHE [*]
;* INVALIDATE_CACHE_ALL
;* FLUSH_ICACHE [*]
;* INVALIDATE_ICACHE_ALL
;* FLUSH_DCACHE [*]
;* INVALIDATE_DCACHE_ALL
;* FLUSH_CACHE_ENTRY
;* FLUSH_ICACHE_ENTRY [*]
;* INVALIDATE_ICACHE_INDEX
;* INVALIDATE_ICACHE_VA
;* FLUSH_DCACHE_ENTRY [*]
;* INVALIDATE_DCACHE_INDEX
;* INVALIDATE_DCACHE_VA
;* INVALIDATE_DCACHE_MVA
;* INVALIDATE_ICACHE_MVA
;* FLUSH_DCACHE_LINE
;* FLUSH_ICACHE_LINE
;* CLEAN_CACHE_ENTRY
;* CLEAN_DCACHE_ENTRY [*]
;* CLEAN_DCACHE_INDEX
;* CLEAN_DCACHE_VA
;* CLEAN_DCACHE_LINE
;* CLEAN_FLUSH_CACHE_ENTRY
;* CLEAN_FLUSH_DCACHE_ENTRY [*]
;* CLEAN_AND_INVALIDATE_DCACHE_INDEX
;* CLEAN_AND_INVALIDATE_DCACHE_VA
;* CLEAN_INVALIDATE_DCACHE_MVA
;* CLEAN_FLUSH_DCACHE_LINE
;* CLEAN_FLUSH_CACHE
;* CLEAN_FLUSH_DCACHE
;* TEST_CLEAN_DCACHE
;* TEST_CLEAN_INVALIDATE_DCACHE
;* ICACHE_PREFETCH
;* DRAIN_WRITEBUFFER
;*
;* CP15 Register8: TLB Functions
;*
;* FLUSH_TLB
;* FLUSH_TLB_ENTRY
;* INVALIDATE_TLB
;* INVALIDATE_TLB_VA
;* INVALIDATE_ITLB
;* INVALIDATE_ITLB_VA
;* INVALIDATE_ITLB_INDEX
;* INVALIDATE_DTLB
;* INVALIDATE_DTLB_VA
;* INVALIDATE_DTLB_INDEX
;* INVALIDATE_UTLB
;* INVALIDATE_UTLB_VA
;* INVALIDATE_DTLB_ASID
;* INVALIDATE_ITLB_ASID
;* INVALIDATE_UTLB_ASID
;*
;* CP15 Register9: Cache Lockdown
;*
;* READ_CACHE_LOCK_DOWN
;* SET_CACHE_NOOF_LOCK_DOWN
;* SET_CACHE_LOCK_DOWN
;* RESET_CACHE_LOCK_DOWN
;* READ_DCACHE_LOCK_INDEX [*]
;* READ_DCACHE_LOCKDOWN_BASE
;* READ_ICACHE_LOCK_INDEX [*]
;* READ_ICACHE_LOCKDOWN_BASE
;* SET_DCACHE_LOCK_DOWN [*]
;* SET_DCACHE_LOCKDOWN
;* RESET_DCACHE_LOCK_DOWN [*]
;* RESET_DCACHE_LOCKDOWN
;* SET_ICACHE_LOCK_DOWN [*]
;* SET_ICACHE_LOCKDOWN
;* RESET_ICACHE_LOCK_DOWN [*]
;* RESET_ICACHE_LOCKDOWN
;* INSTRUCTION_LOCK_DOWN [*]
;* ICACHE_LOCKDOWN
;* DATA_LOCK_DOWN [*]
;* DCACHE_LOCKDOWN
;*
;* CP15 Register10: TLB Lockdown
;*
;* READ_TLB_LOCK_DOWN
;* SET_TLB_NOOF_LOCK_DOWN
;* SET_TLB_LOCK_DOWN
;* READ_ITLB_INDEX
;* WRITE_ITLB_INDEX
;* READ_ITLB_LOCKDOWN
;* WRITE_ITLB_LOCKDOWN
;* WRITE_ITLB_PRESERVE
;* READ_DTLB_INDEX
;* WRITE_DTLB_INDEX
;* READ_DTLB_LOCKDOWN
;* WRITE_DTLB_LOCKDOWN
;* WRITE_DTLB_PRESERVE
;* READ_UTLB_INDEX
;* WRITE_UTLB_INDEX
;* WRITE_UTLB_PRESERVE
;*
;* CP15 Register15: Test/Debug
;*
;* DYNCLK_ON
;* DYNCLK_OFF
;* SYNCLK_ON
;* SYNCLK_OFF
;* SET_FCLK_SOURCE
;* WRITE_MMU_DEBUG_CTRL_REG
;*
;*******************************************************************************
INCLUDE ValUtil-Macros.h.s
;------------------------------------------------------------------------------
; coprocessor declaration
;------------------------------------------------------------------------------
C0 CN 0 ; in case the upper letters are not defined elsewhere
C1 CN 1
C2 CN 2
C3 CN 3
C4 CN 4
C5 CN 5
C6 CN 6
C7 CN 7
C8 CN 8
C9 CN 9
C10 CN 10
C11 CN 11
C12 CN 12
C13 CN 13
C14 CN 14
C15 CN 15
[ ARM_ARCH = 3
; -----------------------------------------------------------
; For Read/Modify/Write of registers which can NOT be read - see Test-Init.s also
; 05/03/98 P Pearse - Register 7 unreadable in arch 4 as well so NOT here
; -----------------------------------------------------------
IMPORT CP15_Reg1_0
IMPORT CP15_Reg2_0
IMPORT CP15_Reg2_1
IMPORT CP15_Reg3_0
SysControl CP 15
TableBase CN 2
DomainReg CN 3 ; Domain already used in e.g. Test mmu/ve5.s
Control CN 1
MACRO
RecordSysCopReg $regnum, $register, $op2
; -----------------------------------------------------------
; Store what we think the current value of the relevent syatem coprocessor register is
; $regnum System coprocessor concerned - 1/2/3
; $register Register in which value just (hopefully) written to system coprocessor register is held - r0 to r12
; $op2 Allows opcode 2 in the MRC instruction to be varied - 0/1
; 05/03/98 P Pearse
; -----------------------------------------------------------
LOCAL
B Past$l
LCLS AddReg ; Default address register is r0
AddReg SETS "r0" ; - if r0 has the value to write then use r1
[ "r0" = "$register" :LOR: "R0" = "$register"
AddReg SETS "r1"
]
Store_AddReg$l DCD 0
Past$l
STR $AddReg,Store_AddReg$l ; Save current value in addressing register
LCLS opc ; Take character value of op2
opc SETS "$op2":RIGHT:1
LDR $AddReg, =CP15_Reg$regnum._$opc
STR $register,[$AddReg]
LDR $AddReg,Store_AddReg$l ; Retrieve original value to addressing register
LOCAL_END
MEND
MACRO
RetrieveSysCopReg $regnum, $register, $op2
; -----------------------------------------------------------
; Retrieve what we think the current value of the relevent system coprocessor register is
; $regnum System coprocessor concerned - 1/2/3
; $register Reg to which latest value of system coprocessor register is to be written - r0 to r12
; $op2 Allows opcode 2 in the MRC instruction to be varied - 0/1
; 05/03/98 P Pearse
; -----------------------------------------------------------
LOCAL
B Past$l
LCLS AddReg ; Default address register is r0
AddReg SETS "r0" ; - if r0 has the value to write then use r1
[ "r0" = "$register" :LOR: "R0" = "$register"
AddReg SETS "r1"
]
Store_AddReg$l DCD 0
Past$l
STR $AddReg,Store_AddReg$l ; Save current value in addressing register
LCLS opc ; Take character value of op2
opc SETS "$op2":RIGHT:1
LDR $AddReg, =CP15_Reg$regnum._$opc
LDR $register,[$AddReg]
LDR $AddReg,Store_AddReg$l ; Retrieve original value to addressing register
LOCAL_END
MEND
] ; End arch 3 oly
MACRO
CheckUnreadableCopReg $regnum
; -----------------------------------------------------------
; Check valid system coprocessor unreadable register
; $regnum - system coprocessor register - 1/2/3
; 05/03/98 P Pearse
; -----------------------------------------------------------
[ $regnum /= 1 :LAND: $regnum /= 2 :LAND: $regnum /= 3
! 1, "Use only for c1, c2, c3 (regnum 1,2,3) "
]
MEND
MACRO
$label ReadCoprocReg $regnum, $register, $op2 = ""
; -----------------------------------------------------------
; Read system coprocessor register
; - for architecture 3 this register is unreadable so a storage location in the code area is used
; in an attempt to keep track of the current register value
; $regnum System coprocessor concerned - 1/2/3
; $register Reg into which latest value written to system coprocessor register is to be placed - r0 to r12
; $op2 = "" Allows opcode 2 in the MRC instruction to be varied, defaults to 0 - 0/1
; 05/03/98 P Pearse
; -----------------------------------------------------------
LCLA opcode_2
opcode_2 SETA 0
[ "$op2" /= ""
[ $op2 /= 0 :LAND: $op2 /= 1
! 1, "Only implemented for opcode2 values: 0 or 1"
]
opcode_2 SETA $op2
]
CheckUnreadableCopReg $regnum
[ ARM_ARCH >=4
; -----------------------------------------------------------
; Under architecture 4 and higher we can read this register
; -----------------------------------------------------------
$label MRC p15, 0, $register, c$regnum, c0, $opcode_2
|
; -----------------------------------------------------------
; Under architecture 3 we can NOT read this register
; -----------------------------------------------------------
! 0,"WARNING: Reading this coprocessor register is UNPREDICTABLE in architecture 3"
! 0," Using Record/RetrieveSysCopReg to implement read/modify/write"
$label RetrieveSysCopReg $regnum, $register, $opcode_2
]
MEND
MACRO
$label WriteCoprocReg $regnum, $register, $op2 = ""
; -----------------------------------------------------------
; Write system coprocessor register
; - for architecture 3 this register is unreadable so a storage location in the code area is used
; in an attempt to keep track of the current register value
; $regnum System coprocessor concerned - 1/2/3
; $register Reg in which latest value written to system coprocessor register is held - r0 to r12
; $op2 = "" Allows opcode 2 in the MRC instruction to be varied, defaults to 0 - 0/1
; 05/03/98 P Pearse
; -----------------------------------------------------------
LCLA opcode_2
opcode_2 SETA 0
[ "$op2" /= ""
[ $op2 /= 0 :LAND: $op2 /= 1
! 1, "Only implemented for opcode2 values: 0 or 1"
]
opcode_2 SETA $op2
]
CheckUnreadableCopReg $regnum
$label MCR p15, 0, $register, c$regnum, c0, $opcode_2
[ ARM_ARCH = 3
; -----------------------------------------------------------
; Under architecture 3 we can NOT read this register so save its value
; -----------------------------------------------------------
! 0,"WARNING: Reading the Control Reg is UNPREDICTABLE in architecture 3"
! 0," Using Record/RetrieveSysCopReg to implement read/modify/write"
RecordSysCopReg $regnum, $register, $opcode_2
]
MEND
BusErrOn * &0 ; Set a Bus Error address
BusErrOff * &0 ; Unset a Bus Error address
[ TARGET = "710board" :LOR: TARGET = "810board"
TranslationBasePA * &00020000 ; Start of L1 Page Tables
TranslationBaseVA * &03120000 ;
ReadSeq_Params * &0001C000 ; ReadSeq Parameter Block
WriteSeq_Params * &0001C000 ; WriteSeq Parameter Block
MixedSeq_Params * &0001C000 ; MixedSeq Parameter Block
Generic_Params * &0001C000 ; Should be the same as those above
PageTableBase * &00020000
|
TranslationBasePA * &00300000 ; Start of L1 Page Tables
TranslationBaseVA * &03100000 ;
ReadSeq_Params * &00080000 ; ReadSeq Parameter Block
WriteSeq_Params * &00080000 ; WriteSeq Parameter Block
MixedSeq_Params * &00080000 ; MixedSeq Parameter Block
Generic_Params * &00080000 ; Should be the same as those above
PageTableBase * &00200000
]
;*******************************************************************************
; Register0: ID register
;*******************************************************************************
;------------------------------------------------------------------------------
;
; Macro: $label READ_ID_REG $register
;
; Function: Read ID register.
;
MACRO
READ_ID_REG $register
MRC p15, 0, $register, c0, c0, 0
MEND
;------------------------------------------------------------------------------
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -