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📄 mcbsp2.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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#define            MCBSP2_MCBSP_MCR2_REG_XCBLK_NUMB                                                                      3
#define            MCBSP2_MCBSP_MCR2_REG_XCBLK_RES_VAL                                                                   0x0
//R

#define            MCBSP2_MCBSP_MCR2_REG_XMCM_POS                                                                        0
#define            MCBSP2_MCBSP_MCR2_REG_XMCM_NUMB                                                                       2
#define            MCBSP2_MCBSP_MCR2_REG_XMCM_RES_VAL                                                                    0x0
//R/W


//MCBSP2_MCBSP_MCR1_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_MCR1_REG                                                                               REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_MCR1_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_MCR1_REG                                                                               REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_MCR1_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_MCR1_REG_RSVD1_POS                                                                       10
#define            MCBSP2_MCBSP_MCR1_REG_RSVD1_NUMB                                                                      6
#define            MCBSP2_MCBSP_MCR1_REG_RSVD1_RES_VAL                                                                   0x0
//R

#define            MCBSP2_MCBSP_MCR1_REG_RMCME_POS                                                                       9
#define            MCBSP2_MCBSP_MCR1_REG_RMCME_NUMB                                                                      1
#define            MCBSP2_MCBSP_MCR1_REG_RMCME_RES_VAL                                                                   0x0
//R/W

#define            MCBSP2_MCBSP_MCR1_REG_RPBBLK_POS                                                                      7
#define            MCBSP2_MCBSP_MCR1_REG_RPBBLK_NUMB                                                                     2
#define            MCBSP2_MCBSP_MCR1_REG_RPBBLK_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_MCR1_REG_RPABLK_POS                                                                      5
#define            MCBSP2_MCBSP_MCR1_REG_RPABLK_NUMB                                                                     2
#define            MCBSP2_MCBSP_MCR1_REG_RPABLK_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_MCR1_REG_RCBLK_POS                                                                       2
#define            MCBSP2_MCBSP_MCR1_REG_RCBLK_NUMB                                                                      3
#define            MCBSP2_MCBSP_MCR1_REG_RCBLK_RES_VAL                                                                   0x0
//R

#define            MCBSP2_MCBSP_MCR1_REG_RSVD2_POS                                                                       1
#define            MCBSP2_MCBSP_MCR1_REG_RSVD2_NUMB                                                                      1
#define            MCBSP2_MCBSP_MCR1_REG_RSVD2_RES_VAL                                                                   0x0
//R

#define            MCBSP2_MCBSP_MCR1_REG_RMCM_POS                                                                        0
#define            MCBSP2_MCBSP_MCR1_REG_RMCM_NUMB                                                                       1
#define            MCBSP2_MCBSP_MCR1_REG_RMCM_RES_VAL                                                                    0x0
//R/W


//MCBSP2_MCBSP_RCERA_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_RCERA_REG                                                                              REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCERA_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_RCERA_REG                                                                              REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCERA_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_RCERA_REG_RCERA_POS                                                                      0
#define            MCBSP2_MCBSP_RCERA_REG_RCERA_NUMB                                                                     16
#define            MCBSP2_MCBSP_RCERA_REG_RCERA_RES_VAL                                                                  0x0
//R/W


//MCBSP2_MCBSP_RCERB_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_RCERB_REG                                                                              REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCERB_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_RCERB_REG                                                                              REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCERB_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_RCERB_REG_RCERB_POS                                                                      0
#define            MCBSP2_MCBSP_RCERB_REG_RCERB_NUMB                                                                     16
#define            MCBSP2_MCBSP_RCERB_REG_RCERB_RES_VAL                                                                  0x0
//R/W


//MCBSP2_MCBSP_XCERA_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_XCERA_REG                                                                              REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCERA_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_XCERA_REG                                                                              REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCERA_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_XCERA_REG_XCERA_POS                                                                      0
#define            MCBSP2_MCBSP_XCERA_REG_XCERA_NUMB                                                                     16
#define            MCBSP2_MCBSP_XCERA_REG_XCERA_RES_VAL                                                                  0x0
//R/W


//MCBSP2_MCBSP_XCERB_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_XCERB_REG                                                                              REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCERB_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_XCERB_REG                                                                              REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCERB_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_XCERB_REG_XCERB_POS                                                                      0
#define            MCBSP2_MCBSP_XCERB_REG_XCERB_NUMB                                                                     16
#define            MCBSP2_MCBSP_XCERB_REG_XCERB_RES_VAL                                                                  0x0
//R/W


//MCBSP2_MCBSP_PCR_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_PCR_REG                                                                                REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_PCR_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_PCR_REG                                                                                REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_PCR_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_PCR_REG_RSVD_POS                                                                         15
#define            MCBSP2_MCBSP_PCR_REG_RSVD_NUMB                                                                        1
#define            MCBSP2_MCBSP_PCR_REG_RSVD_RES_VAL                                                                     0x0
//R

#define            MCBSP2_MCBSP_PCR_REG_IDLE_EN_POS                                                                      14
#define            MCBSP2_MCBSP_PCR_REG_IDLE_EN_NUMB                                                                     1
#define            MCBSP2_MCBSP_PCR_REG_IDLE_EN_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_PCR_REG_XIOEN_POS                                                                        13
#define            MCBSP2_MCBSP_PCR_REG_XIOEN_NUMB                                                                       1
#define            MCBSP2_MCBSP_PCR_REG_XIOEN_RES_VAL                                                                    0x0
//R/W

#define            MCBSP2_MCBSP_PCR_REG_RIOEN_POS                                                                        12
#define            MCBSP2_MCBSP_PCR_REG_RIOEN_NUMB                                                                       1
#define            MCBSP2_MCBSP_PCR_REG_RIOEN_RES_VAL                                                                    0x0
//R/W

#define            MCBSP2_MCBSP_PCR_REG_FSXM_POS                                                                         11
#define            MCBSP2_MCBSP_PCR_REG_FSXM_NUMB                                                                        1
#define            MCBSP2_MCBSP_PCR_REG_FSXM_RES_VAL                                                                     0x0
//R/W

#define            MCBSP2_MCBSP_PCR_REG_FSRM_POS                                                                         10
#define            MCBSP2_MCBSP_PCR_REG_FSRM_NUMB                                                                        1
#define            MCBSP2_MCBSP_PCR_REG_FSRM_RES_VAL                                                                     0x0
//R/W

#define            MCBSP2_MCBSP_PCR_REG_CLKXM_POS                                                                        9
#define            MCBSP2_MCBSP_PCR_REG_CLKXM_NUMB                                                                       1
#define            MCBSP2_MCBSP_PCR_REG_CLKXM_RES_VAL                                                                    0x0
//R/W

#define            MCBSP2_MCBSP_PCR_REG_CLKRM_POS                                                                        8
#define            MCBSP2_MCBSP_PCR_REG_CLKRM_NUMB                                                                       1
#define            MCBSP2_MCBSP_PCR_REG_CLKRM_RES_VAL                                                                    0x0
//R/W

#define            MCBSP2_MCBSP_PCR_REG_SCLKME_POS                                                                       7
#define            MCBSP2_MCBSP_PCR_REG_SCLKME_NUMB                                                                      1
#define            MCBSP2_MCBSP_PCR_REG_SCLKME_RES_VAL                                                                   0x0
//R/W

#define            MCBSP2_MCBSP_PCR_REG_CLKS_STAT_POS                                                                    6
#define            MCBSP2_MCBSP_PCR_REG_CLKS_STAT_NUMB                                                                   1
#define            MCBSP2_MCBSP_PCR_REG_CLKS_STAT_RES_VAL                                                                0x0
//R

#define            MCBSP2_MCBSP_PCR_REG_DX_STAT_POS                                                                      5
#define            MCBSP2_MCBSP_PCR_REG_DX_STAT_NUMB                                                                     1
#define            MCBSP2_MCBSP_PCR_REG_DX_STAT_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_PCR_REG_DR_STAT_POS                                                                      4

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