mcbsp2.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define            MCBSP2_MCBSP_RCR1_REG                                                                               REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCR1_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_RCR1_REG                                                                               REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCR1_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_RCR1_REG_RSVD1_POS                                                                       15
#define            MCBSP2_MCBSP_RCR1_REG_RSVD1_NUMB                                                                      1
#define            MCBSP2_MCBSP_RCR1_REG_RSVD1_RES_VAL                                                                   0x0
//R

#define            MCBSP2_MCBSP_RCR1_REG_RFRLEN1_POS                                                                     8
#define            MCBSP2_MCBSP_RCR1_REG_RFRLEN1_NUMB                                                                    7
#define            MCBSP2_MCBSP_RCR1_REG_RFRLEN1_RES_VAL                                                                 0x0
//R/W

#define            MCBSP2_MCBSP_RCR1_REG_RWDLEN1_POS                                                                     5
#define            MCBSP2_MCBSP_RCR1_REG_RWDLEN1_NUMB                                                                    3
#define            MCBSP2_MCBSP_RCR1_REG_RWDLEN1_RES_VAL                                                                 0x0
//R/W

#define            MCBSP2_MCBSP_RCR1_REG_RSVD2_POS                                                                       0
#define            MCBSP2_MCBSP_RCR1_REG_RSVD2_NUMB                                                                      5
#define            MCBSP2_MCBSP_RCR1_REG_RSVD2_RES_VAL                                                                   0x0
//R


//MCBSP2_MCBSP_XCR2_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_XCR2_REG                                                                               REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCR2_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_XCR2_REG                                                                               REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCR2_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_XCR2_REG_XPHASE_POS                                                                      15
#define            MCBSP2_MCBSP_XCR2_REG_XPHASE_NUMB                                                                     1
#define            MCBSP2_MCBSP_XCR2_REG_XPHASE_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_XCR2_REG_XFRLEN2_POS                                                                     8
#define            MCBSP2_MCBSP_XCR2_REG_XFRLEN2_NUMB                                                                    7
#define            MCBSP2_MCBSP_XCR2_REG_XFRLEN2_RES_VAL                                                                 0x0
//R/W

#define            MCBSP2_MCBSP_XCR2_REG_XWDLEN2_POS                                                                     5
#define            MCBSP2_MCBSP_XCR2_REG_XWDLEN2_NUMB                                                                    3
#define            MCBSP2_MCBSP_XCR2_REG_XWDLEN2_RES_VAL                                                                 0x0
//R/W

#define            MCBSP2_MCBSP_XCR2_REG_XCOMPAND_POS                                                                    3
#define            MCBSP2_MCBSP_XCR2_REG_XCOMPAND_NUMB                                                                   2
#define            MCBSP2_MCBSP_XCR2_REG_XCOMPAND_RES_VAL                                                                0x0
//R/W

#define            MCBSP2_MCBSP_XCR2_REG_XFIG_POS                                                                        2
#define            MCBSP2_MCBSP_XCR2_REG_XFIG_NUMB                                                                       1
#define            MCBSP2_MCBSP_XCR2_REG_XFIG_RES_VAL                                                                    0x0
//R/W

#define            MCBSP2_MCBSP_XCR2_REG_XDATDLY_POS                                                                     0
#define            MCBSP2_MCBSP_XCR2_REG_XDATDLY_NUMB                                                                    2
#define            MCBSP2_MCBSP_XCR2_REG_XDATDLY_RES_VAL                                                                 0x0
//R/W


//MCBSP2_MCBSP_XCR1_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_XCR1_REG                                                                               REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCR1_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_XCR1_REG                                                                               REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCR1_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_XCR1_REG_RSVD1_POS                                                                       15
#define            MCBSP2_MCBSP_XCR1_REG_RSVD1_NUMB                                                                      1
#define            MCBSP2_MCBSP_XCR1_REG_RSVD1_RES_VAL                                                                   0x0
//R

#define            MCBSP2_MCBSP_XCR1_REG_XFRLEN1_POS                                                                     8
#define            MCBSP2_MCBSP_XCR1_REG_XFRLEN1_NUMB                                                                    7
#define            MCBSP2_MCBSP_XCR1_REG_XFRLEN1_RES_VAL                                                                 0x0
//R/W

#define            MCBSP2_MCBSP_XCR1_REG_XWDLEN1_POS                                                                     5
#define            MCBSP2_MCBSP_XCR1_REG_XWDLEN1_NUMB                                                                    3
#define            MCBSP2_MCBSP_XCR1_REG_XWDLEN1_RES_VAL                                                                 0x0
//R/W

#define            MCBSP2_MCBSP_XCR1_REG_RSVD2_POS                                                                       0
#define            MCBSP2_MCBSP_XCR1_REG_RSVD2_NUMB                                                                      5
#define            MCBSP2_MCBSP_XCR1_REG_RSVD2_RES_VAL                                                                   0x0
//R


//MCBSP2_MCBSP_SRGR2_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_SRGR2_REG                                                                              REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_SRGR2_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_SRGR2_REG                                                                              REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_SRGR2_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_SRGR2_REG_GSYNC_POS                                                                      15
#define            MCBSP2_MCBSP_SRGR2_REG_GSYNC_NUMB                                                                     1
#define            MCBSP2_MCBSP_SRGR2_REG_GSYNC_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_SRGR2_REG_CLKSP_POS                                                                      14
#define            MCBSP2_MCBSP_SRGR2_REG_CLKSP_NUMB                                                                     1
#define            MCBSP2_MCBSP_SRGR2_REG_CLKSP_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_SRGR2_REG_CLKSM_POS                                                                      13
#define            MCBSP2_MCBSP_SRGR2_REG_CLKSM_NUMB                                                                     1
#define            MCBSP2_MCBSP_SRGR2_REG_CLKSM_RES_VAL                                                                  0x1
//R/W

#define            MCBSP2_MCBSP_SRGR2_REG_FSGM_POS                                                                       12
#define            MCBSP2_MCBSP_SRGR2_REG_FSGM_NUMB                                                                      1
#define            MCBSP2_MCBSP_SRGR2_REG_FSGM_RES_VAL                                                                   0x0
//R/W

#define            MCBSP2_MCBSP_SRGR2_REG_FPER_POS                                                                       0
#define            MCBSP2_MCBSP_SRGR2_REG_FPER_NUMB                                                                      12
#define            MCBSP2_MCBSP_SRGR2_REG_FPER_RES_VAL                                                                   0x0
//R/W


//MCBSP2_MCBSP_SRGR1_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_SRGR1_REG                                                                              REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_SRGR1_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_SRGR1_REG                                                                              REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_SRGR1_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_SRGR1_REG_FWID_POS                                                                       8
#define            MCBSP2_MCBSP_SRGR1_REG_FWID_NUMB                                                                      8
#define            MCBSP2_MCBSP_SRGR1_REG_FWID_RES_VAL                                                                   0x0
//R/W

#define            MCBSP2_MCBSP_SRGR1_REG_CLKGDV_POS                                                                     0
#define            MCBSP2_MCBSP_SRGR1_REG_CLKGDV_NUMB                                                                    8
#define            MCBSP2_MCBSP_SRGR1_REG_CLKGDV_RES_VAL                                                                 0x1
//R/W


//MCBSP2_MCBSP_MCR2_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_MCR2_REG                                                                               REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_MCR2_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_MCR2_REG                                                                               REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_MCR2_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_MCR2_REG_RSVD_POS                                                                        10
#define            MCBSP2_MCBSP_MCR2_REG_RSVD_NUMB                                                                       6
#define            MCBSP2_MCBSP_MCR2_REG_RSVD_RES_VAL                                                                    0x0
//R

#define            MCBSP2_MCBSP_MCR2_REG_XMCME_POS                                                                       9
#define            MCBSP2_MCBSP_MCR2_REG_XMCME_NUMB                                                                      1
#define            MCBSP2_MCBSP_MCR2_REG_XMCME_RES_VAL                                                                   0x0
//R/W

#define            MCBSP2_MCBSP_MCR2_REG_XPBBLK_POS                                                                      7
#define            MCBSP2_MCBSP_MCR2_REG_XPBBLK_NUMB                                                                     2
#define            MCBSP2_MCBSP_MCR2_REG_XPBBLK_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_MCR2_REG_XPABLK_POS                                                                      5
#define            MCBSP2_MCBSP_MCR2_REG_XPABLK_NUMB                                                                     2
#define            MCBSP2_MCBSP_MCR2_REG_XPABLK_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_MCR2_REG_XCBLK_POS                                                                       2