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📄 mcbsp2.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_DXR1_REG                                                                               REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_DXR1_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_DXR1_REG                                                                               REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_DXR1_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_DXR1_REG_DXR1_POS                                                                        0
#define            MCBSP2_MCBSP_DXR1_REG_DXR1_NUMB                                                                       16
#define            MCBSP2_MCBSP_DXR1_REG_DXR1_RES_VAL                                                                    none
//W


//MCBSP2_MCBSP_SPCR2_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_SPCR2_REG                                                                              REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_SPCR2_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_SPCR2_REG                                                                              REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_SPCR2_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_SPCR2_REG_RSVD_POS                                                                       10
#define            MCBSP2_MCBSP_SPCR2_REG_RSVD_NUMB                                                                      6
#define            MCBSP2_MCBSP_SPCR2_REG_RSVD_RES_VAL                                                                   0x0
//R

#define            MCBSP2_MCBSP_SPCR2_REG_FREE_POS                                                                       9
#define            MCBSP2_MCBSP_SPCR2_REG_FREE_NUMB                                                                      1
#define            MCBSP2_MCBSP_SPCR2_REG_FREE_RES_VAL                                                                   0x0
//R/W

#define            MCBSP2_MCBSP_SPCR2_REG_SOFT_POS                                                                       8
#define            MCBSP2_MCBSP_SPCR2_REG_SOFT_NUMB                                                                      1
#define            MCBSP2_MCBSP_SPCR2_REG_SOFT_RES_VAL                                                                   0x0
//R/W

#define            MCBSP2_MCBSP_SPCR2_REG_FRST__POS                                                                      7
#define            MCBSP2_MCBSP_SPCR2_REG_FRST__NUMB                                                                     1
#define            MCBSP2_MCBSP_SPCR2_REG_FRST__RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_SPCR2_REG_GRST__POS                                                                      6
#define            MCBSP2_MCBSP_SPCR2_REG_GRST__NUMB                                                                     1
#define            MCBSP2_MCBSP_SPCR2_REG_GRST__RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_SPCR2_REG_XINTM_POS                                                                      4
#define            MCBSP2_MCBSP_SPCR2_REG_XINTM_NUMB                                                                     2
#define            MCBSP2_MCBSP_SPCR2_REG_XINTM_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_SPCR2_REG_XSYNCERR_POS                                                                   3
#define            MCBSP2_MCBSP_SPCR2_REG_XSYNCERR_NUMB                                                                  1
#define            MCBSP2_MCBSP_SPCR2_REG_XSYNCERR_RES_VAL                                                               0x0
//R/W

#define            MCBSP2_MCBSP_SPCR2_REG_XEMPTY__POS                                                                    2
#define            MCBSP2_MCBSP_SPCR2_REG_XEMPTY__NUMB                                                                   1
#define            MCBSP2_MCBSP_SPCR2_REG_XEMPTY__RES_VAL                                                                0x0
//R

#define            MCBSP2_MCBSP_SPCR2_REG_XRDY_POS                                                                       1
#define            MCBSP2_MCBSP_SPCR2_REG_XRDY_NUMB                                                                      1
#define            MCBSP2_MCBSP_SPCR2_REG_XRDY_RES_VAL                                                                   0x0
//R

#define            MCBSP2_MCBSP_SPCR2_REG_XRST__POS                                                                      0
#define            MCBSP2_MCBSP_SPCR2_REG_XRST__NUMB                                                                     1
#define            MCBSP2_MCBSP_SPCR2_REG_XRST__RES_VAL                                                                  0x0
//R/W


//MCBSP2_MCBSP_SPCR1_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_SPCR1_REG                                                                              REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_SPCR1_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_SPCR1_REG                                                                              REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_SPCR1_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_SPCR1_REG_DLB_POS                                                                        15
#define            MCBSP2_MCBSP_SPCR1_REG_DLB_NUMB                                                                       1
#define            MCBSP2_MCBSP_SPCR1_REG_DLB_RES_VAL                                                                    0x0
//R/W

#define            MCBSP2_MCBSP_SPCR1_REG_RJUST_POS                                                                      13
#define            MCBSP2_MCBSP_SPCR1_REG_RJUST_NUMB                                                                     2
#define            MCBSP2_MCBSP_SPCR1_REG_RJUST_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_SPCR1_REG_CLKSTP_POS                                                                     11
#define            MCBSP2_MCBSP_SPCR1_REG_CLKSTP_NUMB                                                                    2
#define            MCBSP2_MCBSP_SPCR1_REG_CLKSTP_RES_VAL                                                                 0x0
//R/W

#define            MCBSP2_MCBSP_SPCR1_REG_RSVD_POS                                                                       8
#define            MCBSP2_MCBSP_SPCR1_REG_RSVD_NUMB                                                                      3
#define            MCBSP2_MCBSP_SPCR1_REG_RSVD_RES_VAL                                                                   0x0
//R

#define            MCBSP2_MCBSP_SPCR1_REG_DXENA_POS                                                                      7
#define            MCBSP2_MCBSP_SPCR1_REG_DXENA_NUMB                                                                     1
#define            MCBSP2_MCBSP_SPCR1_REG_DXENA_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_SPCR1_REG_ABIS_POS                                                                       6
#define            MCBSP2_MCBSP_SPCR1_REG_ABIS_NUMB                                                                      1
#define            MCBSP2_MCBSP_SPCR1_REG_ABIS_RES_VAL                                                                   0x0
//R/W

#define            MCBSP2_MCBSP_SPCR1_REG_RINTM_POS                                                                      4
#define            MCBSP2_MCBSP_SPCR1_REG_RINTM_NUMB                                                                     2
#define            MCBSP2_MCBSP_SPCR1_REG_RINTM_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_SPCR1_REG_RSYNCERR_POS                                                                   3
#define            MCBSP2_MCBSP_SPCR1_REG_RSYNCERR_NUMB                                                                  1
#define            MCBSP2_MCBSP_SPCR1_REG_RSYNCERR_RES_VAL                                                               0x0
//R/W

#define            MCBSP2_MCBSP_SPCR1_REG_RFULL_POS                                                                      2
#define            MCBSP2_MCBSP_SPCR1_REG_RFULL_NUMB                                                                     1
#define            MCBSP2_MCBSP_SPCR1_REG_RFULL_RES_VAL                                                                  0x0
//R

#define            MCBSP2_MCBSP_SPCR1_REG_RRDY_POS                                                                       1
#define            MCBSP2_MCBSP_SPCR1_REG_RRDY_NUMB                                                                      1
#define            MCBSP2_MCBSP_SPCR1_REG_RRDY_RES_VAL                                                                   0x0
//R

#define            MCBSP2_MCBSP_SPCR1_REG_RRST__POS                                                                      0
#define            MCBSP2_MCBSP_SPCR1_REG_RRST__NUMB                                                                     1
#define            MCBSP2_MCBSP_SPCR1_REG_RRST__RES_VAL                                                                  0x0
//R/W


//MCBSP2_MCBSP_RCR2_REG



#ifndef DSP_ACCESS
#define            MCBSP2_MCBSP_RCR2_REG                                                                               REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCR2_REG_OFFSET)
#else
#define            MCBSP2_MCBSP_RCR2_REG                                                                               REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCR2_REG_OFFSET)
#endif


#define            MCBSP2_MCBSP_RCR2_REG_RPHASE_POS                                                                      15
#define            MCBSP2_MCBSP_RCR2_REG_RPHASE_NUMB                                                                     1
#define            MCBSP2_MCBSP_RCR2_REG_RPHASE_RES_VAL                                                                  0x0
//R/W

#define            MCBSP2_MCBSP_RCR2_REG_RFRLEN2_POS                                                                     8
#define            MCBSP2_MCBSP_RCR2_REG_RFRLEN2_NUMB                                                                    7
#define            MCBSP2_MCBSP_RCR2_REG_RFRLEN2_RES_VAL                                                                 0x0
//R/W

#define            MCBSP2_MCBSP_RCR2_REG_RWDLEN2_POS                                                                     5
#define            MCBSP2_MCBSP_RCR2_REG_RWDLEN2_NUMB                                                                    3
#define            MCBSP2_MCBSP_RCR2_REG_RWDLEN2_RES_VAL                                                                 0x0
//R/W

#define            MCBSP2_MCBSP_RCR2_REG_RCOMPAND_POS                                                                    3
#define            MCBSP2_MCBSP_RCR2_REG_RCOMPAND_NUMB                                                                   2
#define            MCBSP2_MCBSP_RCR2_REG_RCOMPAND_RES_VAL                                                                0x0
//R/W

#define            MCBSP2_MCBSP_RCR2_REG_RFIG_POS                                                                        2
#define            MCBSP2_MCBSP_RCR2_REG_RFIG_NUMB                                                                       1
#define            MCBSP2_MCBSP_RCR2_REG_RFIG_RES_VAL                                                                    0x0
//R/W

#define            MCBSP2_MCBSP_RCR2_REG_RDATDLY_POS                                                                     0
#define            MCBSP2_MCBSP_RCR2_REG_RDATDLY_NUMB                                                                    2
#define            MCBSP2_MCBSP_RCR2_REG_RDATDLY_RES_VAL                                                                 0x0
//R/W


//MCBSP2_MCBSP_RCR1_REG



#ifndef DSP_ACCESS

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