📄 mcbsp2.h
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/*Header modified by DSP-CONVERT V1.01 Script on Tue Aug 13 14:51:43 MEST 2002*/
//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :mcbsp2.h
//
// Date of Module Modification:5/29/02
// Date of Generation :6/19/02
//
//
//========================================================================
#ifndef _MCBSP2__H
#define _MCBSP2__H
#include "mapping.h"
#include "global_types.h"
#include "clkrst.h"
#include "reset.h"
#include "mcbsp.h"
#include "errorcodes.h"
//BEGIN INC GENERATION
//--------------------------------------
#ifndef DSP_ADJUST /* If DSP_ADJUST is not defined, we are using */
#define DSP_ADJUST /* include file for ARM code, we do not need any */
#endif /* modufucations. If this file is used for DSP code, */
//Register Offset
//-------------------
#define MCBSP2_MCBSP_DRR2_REG_OFFSET (0x00 DSP_ADJUST)
#define MCBSP2_MCBSP_DRR1_REG_OFFSET (0x02 DSP_ADJUST)
#define MCBSP2_MCBSP_DXR2_REG_OFFSET (0x04 DSP_ADJUST)
#define MCBSP2_MCBSP_DXR1_REG_OFFSET (0x06 DSP_ADJUST)
#define MCBSP2_MCBSP_SPCR2_REG_OFFSET (0x08 DSP_ADJUST)
#define MCBSP2_MCBSP_SPCR1_REG_OFFSET (0x0A DSP_ADJUST)
#define MCBSP2_MCBSP_RCR2_REG_OFFSET (0x0C DSP_ADJUST)
#define MCBSP2_MCBSP_RCR1_REG_OFFSET (0x0E DSP_ADJUST)
#define MCBSP2_MCBSP_XCR2_REG_OFFSET (0x10 DSP_ADJUST)
#define MCBSP2_MCBSP_XCR1_REG_OFFSET (0x12 DSP_ADJUST)
#define MCBSP2_MCBSP_SRGR2_REG_OFFSET (0x14 DSP_ADJUST)
#define MCBSP2_MCBSP_SRGR1_REG_OFFSET (0x16 DSP_ADJUST)
#define MCBSP2_MCBSP_MCR2_REG_OFFSET (0x18 DSP_ADJUST)
#define MCBSP2_MCBSP_MCR1_REG_OFFSET (0x1A DSP_ADJUST)
#define MCBSP2_MCBSP_RCERA_REG_OFFSET (0x1C DSP_ADJUST)
#define MCBSP2_MCBSP_RCERB_REG_OFFSET (0x1E DSP_ADJUST)
#define MCBSP2_MCBSP_XCERA_REG_OFFSET (0x20 DSP_ADJUST)
#define MCBSP2_MCBSP_XCERB_REG_OFFSET (0x22 DSP_ADJUST)
#define MCBSP2_MCBSP_PCR_REG_OFFSET (0x24 DSP_ADJUST)
#define MCBSP2_MCBSP_RCERC_REG_OFFSET (0x26 DSP_ADJUST)
#define MCBSP2_MCBSP_RCERD_REG_OFFSET (0x28 DSP_ADJUST)
#define MCBSP2_MCBSP_XCERC_REG_OFFSET (0x2A DSP_ADJUST)
#define MCBSP2_MCBSP_XCERD_REG_OFFSET (0x2C DSP_ADJUST)
#define MCBSP2_MCBSP_RCERE_REG_OFFSET (0x2E DSP_ADJUST)
#define MCBSP2_MCBSP_RCERF_REG_OFFSET (0x30 DSP_ADJUST)
#define MCBSP2_MCBSP_XCERE_REG_OFFSET (0x32 DSP_ADJUST)
#define MCBSP2_MCBSP_XCERF_REG_OFFSET (0x34 DSP_ADJUST)
#define MCBSP2_MCBSP_RCERG_REG_OFFSET (0x36 DSP_ADJUST)
#define MCBSP2_MCBSP_RCERH_REG_OFFSET (0x38 DSP_ADJUST)
#define MCBSP2_MCBSP_XCERG_REG_OFFSET (0x3A DSP_ADJUST)
#define MCBSP2_MCBSP_XCERH_REG_OFFSET (0x3C DSP_ADJUST)
#define MCBSP2_MCBSP_REV_REG_OFFSET (0x3E DSP_ADJUST)
//Register Address
//-------------------
#ifndef DSP_ACCESS
#define MCBSP2_MCBSP_DRR2_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_DRR2_REG_OFFSET)
#define MCBSP2_MCBSP_DRR1_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_DRR1_REG_OFFSET)
#define MCBSP2_MCBSP_DXR2_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_DXR2_REG_OFFSET)
#define MCBSP2_MCBSP_DXR1_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_DXR1_REG_OFFSET)
#define MCBSP2_MCBSP_SPCR2_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_SPCR2_REG_OFFSET)
#define MCBSP2_MCBSP_SPCR1_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_SPCR1_REG_OFFSET)
#define MCBSP2_MCBSP_RCR2_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCR2_REG_OFFSET)
#define MCBSP2_MCBSP_RCR1_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCR1_REG_OFFSET)
#define MCBSP2_MCBSP_XCR2_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCR2_REG_OFFSET)
#define MCBSP2_MCBSP_XCR1_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCR1_REG_OFFSET)
#define MCBSP2_MCBSP_SRGR2_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_SRGR2_REG_OFFSET)
#define MCBSP2_MCBSP_SRGR1_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_SRGR1_REG_OFFSET)
#define MCBSP2_MCBSP_MCR2_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_MCR2_REG_OFFSET)
#define MCBSP2_MCBSP_MCR1_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_MCR1_REG_OFFSET)
#define MCBSP2_MCBSP_RCERA_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCERA_REG_OFFSET)
#define MCBSP2_MCBSP_RCERB_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCERB_REG_OFFSET)
#define MCBSP2_MCBSP_XCERA_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCERA_REG_OFFSET)
#define MCBSP2_MCBSP_XCERB_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCERB_REG_OFFSET)
#define MCBSP2_MCBSP_PCR_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_PCR_REG_OFFSET)
#define MCBSP2_MCBSP_RCERC_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCERC_REG_OFFSET)
#define MCBSP2_MCBSP_RCERD_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCERD_REG_OFFSET)
#define MCBSP2_MCBSP_XCERC_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCERC_REG_OFFSET)
#define MCBSP2_MCBSP_XCERD_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCERD_REG_OFFSET)
#define MCBSP2_MCBSP_RCERE_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCERE_REG_OFFSET)
#define MCBSP2_MCBSP_RCERF_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCERF_REG_OFFSET)
#define MCBSP2_MCBSP_XCERE_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCERE_REG_OFFSET)
#define MCBSP2_MCBSP_XCERF_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCERF_REG_OFFSET)
#define MCBSP2_MCBSP_RCERG_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCERG_REG_OFFSET)
#define MCBSP2_MCBSP_RCERH_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_RCERH_REG_OFFSET)
#define MCBSP2_MCBSP_XCERG_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCERG_REG_OFFSET)
#define MCBSP2_MCBSP_XCERH_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_XCERH_REG_OFFSET)
#define MCBSP2_MCBSP_REV_ADD (MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_REV_REG_OFFSET)
#else
#define MCBSP2_MCBSP_DRR2_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_DRR2_REG_OFFSET)
#define MCBSP2_MCBSP_DRR1_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_DRR1_REG_OFFSET)
#define MCBSP2_MCBSP_DXR2_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_DXR2_REG_OFFSET)
#define MCBSP2_MCBSP_DXR1_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_DXR1_REG_OFFSET)
#define MCBSP2_MCBSP_SPCR2_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_SPCR2_REG_OFFSET)
#define MCBSP2_MCBSP_SPCR1_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_SPCR1_REG_OFFSET)
#define MCBSP2_MCBSP_RCR2_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCR2_REG_OFFSET)
#define MCBSP2_MCBSP_RCR1_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCR1_REG_OFFSET)
#define MCBSP2_MCBSP_XCR2_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCR2_REG_OFFSET)
#define MCBSP2_MCBSP_XCR1_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCR1_REG_OFFSET)
#define MCBSP2_MCBSP_SRGR2_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_SRGR2_REG_OFFSET)
#define MCBSP2_MCBSP_SRGR1_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_SRGR1_REG_OFFSET)
#define MCBSP2_MCBSP_MCR2_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_MCR2_REG_OFFSET)
#define MCBSP2_MCBSP_MCR1_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_MCR1_REG_OFFSET)
#define MCBSP2_MCBSP_RCERA_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCERA_REG_OFFSET)
#define MCBSP2_MCBSP_RCERB_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCERB_REG_OFFSET)
#define MCBSP2_MCBSP_XCERA_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCERA_REG_OFFSET)
#define MCBSP2_MCBSP_XCERB_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCERB_REG_OFFSET)
#define MCBSP2_MCBSP_PCR_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_PCR_REG_OFFSET)
#define MCBSP2_MCBSP_RCERC_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCERC_REG_OFFSET)
#define MCBSP2_MCBSP_RCERD_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCERD_REG_OFFSET)
#define MCBSP2_MCBSP_XCERC_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCERC_REG_OFFSET)
#define MCBSP2_MCBSP_XCERD_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCERD_REG_OFFSET)
#define MCBSP2_MCBSP_RCERE_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCERE_REG_OFFSET)
#define MCBSP2_MCBSP_RCERF_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCERF_REG_OFFSET)
#define MCBSP2_MCBSP_XCERE_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCERE_REG_OFFSET)
#define MCBSP2_MCBSP_XCERF_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCERF_REG_OFFSET)
#define MCBSP2_MCBSP_RCERG_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCERG_REG_OFFSET)
#define MCBSP2_MCBSP_RCERH_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_RCERH_REG_OFFSET)
#define MCBSP2_MCBSP_XCERG_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCERG_REG_OFFSET)
#define MCBSP2_MCBSP_XCERH_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_XCERH_REG_OFFSET)
#define MCBSP2_MCBSP_REV_ADD (MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_REV_REG_OFFSET)
#endif /* DSP_ACCESS */
#ifndef DSP_ACCESS
#define MCBSP2_MCBSP_DRR2_REG REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_DRR2_REG_OFFSET)
#else
#define MCBSP2_MCBSP_DRR2_REG REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_DRR2_REG_OFFSET)
#endif
#define MCBSP2_MCBSP_DRR2_REG_DRR2_POS 0
#define MCBSP2_MCBSP_DRR2_REG_DRR2_NUMB 16
#define MCBSP2_MCBSP_DRR2_REG_DRR2_RES_VAL none
//R
//MCBSP2_MCBSP_DRR1_REG
#ifndef DSP_ACCESS
#define MCBSP2_MCBSP_DRR1_REG REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_DRR1_REG_OFFSET)
#else
#define MCBSP2_MCBSP_DRR1_REG REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_DRR1_REG_OFFSET)
#endif
#define MCBSP2_MCBSP_DRR1_REG_DRR1_POS 0
#define MCBSP2_MCBSP_DRR1_REG_DRR1_NUMB 16
#define MCBSP2_MCBSP_DRR1_REG_DRR1_RES_VAL none
//R
//MCBSP2_MCBSP_DXR2_REG
#ifndef DSP_ACCESS
#define MCBSP2_MCBSP_DXR2_REG REG16(MCBSP2_BASE_ADDR_ARM+MCBSP2_MCBSP_DXR2_REG_OFFSET)
#else
#define MCBSP2_MCBSP_DXR2_REG REG16(MCBSP2_BASE_ADDR_DSP+MCBSP2_MCBSP_DXR2_REG_OFFSET)
#endif
#define MCBSP2_MCBSP_DXR2_REG_DXR2_POS 0
#define MCBSP2_MCBSP_DXR2_REG_DXR2_NUMB 16
#define MCBSP2_MCBSP_DXR2_REG_DXR2_RES_VAL none
//W
//MCBSP2_MCBSP_DXR1_REG
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