📄 configuration.h
字号:
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_09_POS 10
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_09_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_09_RES_VAL 0x08
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_08_POS 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_08_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_08_RES_VAL 0x07
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_07_POS 0
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_07_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_07_RES_VAL 0x06
//R/W
//CONFIGURATION_FUNC_MUX_DSP_DMA_C
//-------------------
#define CONFIGURATION_FUNC_MUX_DSP_DMA_C REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_DSP_DMA_C_OFFSET)
//CONFIGURATION_FUNC_MUX_DSP_DMA_D
//-------------------
#define CONFIGURATION_FUNC_MUX_DSP_DMA_D REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_DSP_DMA_D_OFFSET)
//CONFIGURATION_FUNC_MUX_ARM_DMA_A
//-------------------
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_ARM_DMA_A_OFFSET)
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_05_POS 30
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_05_NUMB 2
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_05_RES_VAL 0x04
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_04_POS 18
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_04_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_04_RES_VAL 0x03
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_03_POS 12
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_03_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_03_RES_VAL 0x02
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_02_POS 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_02_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_02_RES_VAL 0x01
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_01_POS 0
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_01_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_CONF_ARM_DMA_REQ_01_RES_VAL 0x00
//R/W
//CONFIGURATION_FUNC_MUX_ARM_DMA_B
//-------------------
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_ARM_DMA_B_OFFSET)
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_RESERVED_POS 30
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_RESERVED_NUMB 2
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_RESERVED_RES_VAL 0x0
//R
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_10_POS 24
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_10_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_10_RES_VAL 0x09
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_09_POS 18
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_09_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_09_RES_VAL 0x08
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_08_POS 12
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_08_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_08_RES_VAL 0x07
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_07_POS 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_07_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_07_RES_VAL 0x06
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_06_POS 0
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_06_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_CONF_ARM_DMA_REQ_06_RES_VAL 0x05
//R/W
//CONFIGURATION_FUNC_MUX_ARM_DMA_C
//-------------------
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_ARM_DMA_C_OFFSET)
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_RESERVED_POS 30
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_RESERVED_NUMB 2
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_RESERVED_RES_VAL 0x0
//R
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_15_POS 24
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_15_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_15_RES_VAL 0x0E
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_14_POS 18
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_14_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_14_RES_VAL 0x0D
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_13_POS 12
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_13_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_13_RES_VAL 0x0C
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_12_POS 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_12_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_12_RES_VAL 0x0B
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_11_POS 0
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_11_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_CONF_ARM_DMA_REQ_11_RES_VAL 0x0A
//R/W
//CONFIGURATION_FUNC_MUX_ARM_DMA_D
//-------------------
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_ARM_DMA_D_OFFSET)
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_RESERVED_POS 30
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_RESERVED_NUMB 2
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_RESERVED_RES_VAL 0x0
//R
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_20_POS 24
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_20_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_20_RES_VAL 0x13
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_19_POS 18
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_19_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_19_RES_VAL 0x12
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_18_POS 12
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_18_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_18_RES_VAL 0x11
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_17_POS 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_17_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_17_RES_VAL 0x10
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_16_POS 0
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_16_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_CONF_ARM_DMA_REQ_16_RES_VAL 0x0F
//R/W
//CONFIGURATION_FUNC_MUX_ARM_DMA_E
//-------------------
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_ARM_DMA_E_OFFSET)
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_RESERVED_POS 30
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_RESERVED_NUMB 2
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_RESERVED_RES_VAL 0x0
//R
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_25_POS 24
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_25_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_25_RES_VAL 0x18
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_24_POS 18
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_24_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_24_RES_VAL 0x17
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_23_POS 12
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_23_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_23_RES_VAL 0x16
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_22_POS 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_22_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_22_RES_VAL 0x15
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_21_POS 0
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_21_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_CONF_ARM_DMA_REQ_21_RES_VAL 0x14
//R/W
//CONFIGURATION_FUNC_MUX_ARM_DMA_F
//-------------------
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_ARM_DMA_F_OFFSET)
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_RESERVED_POS 30
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_RESERVED_NUMB 2
//#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_RESERVED_RES_VAL 0x0
//R
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_30_POS 24
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_30_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_30_RES_VAL 0x1D
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_29_POS 18
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_29_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_29_RES_VAL 0x1C
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_28_POS 12
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_28_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_28_RES_VAL 0x1B
//R/W
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_27_POS 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_27_NUMB 6
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_CONF_ARM_DMA_REQ_27_RES_VAL 0x1A
//R/W
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -