📄 configuration.h
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//CONFIGURATION_VOLTAGE_CTRL_0
//-------------------
#define CONFIGURATION_VOLTAGE_CTRL_0 REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_VOLTAGE_CTRL_0_OFFSET)
//#define CONFIGURATION_VOLTAGE_CTRL_0_RESERVED_POS 14
//#define CONFIGURATION_VOLTAGE_CTRL_0_RESERVED_NUMB 18
//#define CONFIGURATION_VOLTAGE_CTRL_0_RESERVED_RES_VAL 0x0
//R/W
#define CONFIGURATION_VOLTAGE_CTRL_0_SUBLVDS_CONF_VALID_R_POS 13
#define CONFIGURATION_VOLTAGE_CTRL_0_SUBLVDS_CONF_VALID_R_NUMB 1
#define CONFIGURATION_VOLTAGE_CTRL_0_SUBLVDS_CONF_VALID_R_RES_VAL 0X0
//R/W
//#define CONFIGURATION_VOLTAGE_CTRL_0_RESERVED_POS 8
//#define CONFIGURATION_VOLTAGE_CTRL_0_RESERVED_NUMB 5
//#define CONFIGURATION_VOLTAGE_CTRL_0_RESERVED_RES_VAL 0x0
//R/W
#define CONFIGURATION_VOLTAGE_CTRL_0_MMC1_PWRDN_POS 7
#define CONFIGURATION_VOLTAGE_CTRL_0_MMC1_PWRDN_NUMB 1
#define CONFIGURATION_VOLTAGE_CTRL_0_MMC1_PWRDN_RES_VAL 0x0
//R/W
#define CONFIGURATION_VOLTAGE_CTRL_0_USIM_PWRDN_POS 6
#define CONFIGURATION_VOLTAGE_CTRL_0_USIM_PWRDN_NUMB 1
#define CONFIGURATION_VOLTAGE_CTRL_0_USIM_PWRDN_RES_VAL 0x0
//R/W
#define CONFIGURATION_VOLTAGE_CTRL_0_MMC_PBIAS_CTL_POS 3
#define CONFIGURATION_VOLTAGE_CTRL_0_MMC_PBIAS_CTL_NUMB 3
#define CONFIGURATION_VOLTAGE_CTRL_0_MMC_PBIAS_CTL_RES_VAL 0x000
//R/W
#define CONFIGURATION_VOLTAGE_CTRL_0_USIM_PBIAS_CTL_POS 0
#define CONFIGURATION_VOLTAGE_CTRL_0_USIM_PBIAS_CTL_NUMB 3
#define CONFIGURATION_VOLTAGE_CTRL_0_USIM_PBIAS_CTL_RES_VAL 0x000
//R/W
//CONFIGURATION_USB_TRANSCEIVER_CTRL
//-------------------
#define CONFIGURATION_USB_TRANSCEIVER_CTRL REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_USB_TRANSCEIVER_CTRL_OFFSET)
//#define CONFIGURATION_USB_TRANSCEIVER_CTRL_RESERVED_POS 16
//#define CONFIGURATION_USB_TRANSCEIVER_CTRL_RESERVED_NUMB 16
//#define CONFIGURATION_USB_TRANSCEIVER_CTRL_RESERVED_RES_VAL 0x0
//R
#define CONFIGURATION_USB_TRANSCEIVER_CTRL_USB2_WRMODE_POS 14
#define CONFIGURATION_USB_TRANSCEIVER_CTRL_USB2_WRMODE_NUMB 2
#define CONFIGURATION_USB_TRANSCEIVER_CTRL_USB2_WRMODE_RES_VAL 0x0
//R/W
#define CONFIGURATION_USB_TRANSCEIVER_CTRL_USB1_WRMODE_POS 12
#define CONFIGURATION_USB_TRANSCEIVER_CTRL_USB1_WRMODE_NUMB 2
#define CONFIGURATION_USB_TRANSCEIVER_CTRL_USB1_WRMODE_RES_VAL 0x0
//R/W
#define CONFIGURATION_USB_TRANSCEIVER_CTRL_USB0_WRMODE_POS 10
#define CONFIGURATION_USB_TRANSCEIVER_CTRL_USB0_WRMODE_NUMB 2
#define CONFIGURATION_USB_TRANSCEIVER_CTRL_USB0_WRMODE_RES_VAL 0x0
//R/W
//#define CONFIGURATION_USB_TRANSCEIVER_CTRL_RESERVED_POS 0
//#define CONFIGURATION_USB_TRANSCEIVER_CTRL_RESERVED_NUMB 10
//#define CONFIGURATION_USB_TRANSCEIVER_CTRL_RESERVED_RES_VAL 0x0
//R/W
//CONFIGURATION_TEST_DBG_CTRL_0
//-------------------
#define CONFIGURATION_TEST_DBG_CTRL_0 REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_TEST_DBG_CTRL_0_OFFSET)
//#define CONFIGURATION_TEST_DBG_CTRL_0_RESERVED_POS 22
//#define CONFIGURATION_TEST_DBG_CTRL_0_RESERVED_NUMB 10
//#define CONFIGURATION_TEST_DBG_CTRL_0_RESERVED_RES_VAL 0x0
//R/W
#define CONFIGURATION_TEST_DBG_CTRL_0_CONF_RNG_TEST_OSC_POS 21
#define CONFIGURATION_TEST_DBG_CTRL_0_CONF_RNG_TEST_OSC_NUMB 1
#define CONFIGURATION_TEST_DBG_CTRL_0_CONF_RNG_TEST_OSC_RES_VAL 0x0
//R/W
#define CONFIGURATION_TEST_DBG_CTRL_0_CONF_RNG_SELECT_OSC_POS 20
#define CONFIGURATION_TEST_DBG_CTRL_0_CONF_RNG_SELECT_OSC_NUMB 1
#define CONFIGURATION_TEST_DBG_CTRL_0_CONF_RNG_SELECT_OSC_RES_VAL 0x0
//R/W
//#define CONFIGURATION_TEST_DBG_CTRL_0_RESERVED_POS 4
//#define CONFIGURATION_TEST_DBG_CTRL_0_RESERVED_NUMB 16
//#define CONFIGURATION_TEST_DBG_CTRL_0_RESERVED_RES_VAL 0x0
//R/W
#define CONFIGURATION_TEST_DBG_CTRL_0_CONF_DPLL_EXT_SEL_POS 3
#define CONFIGURATION_TEST_DBG_CTRL_0_CONF_DPLL_EXT_SEL_NUMB 1
#define CONFIGURATION_TEST_DBG_CTRL_0_CONF_DPLL_EXT_SEL_RES_VAL 0x0
//R/W
//#define CONFIGURATION_TEST_DBG_CTRL_0_RESERVED_POS 0
//#define CONFIGURATION_TEST_DBG_CTRL_0_RESERVED_NUMB 3
//#define CONFIGURATION_TEST_DBG_CTRL_0_RESERVED_RES_VAL 0x0
//R
//CONFIGURATION_MOD_CONF_CTRL_0
//-------------------
#define CONFIGURATION_MOD_CONF_CTRL_0 REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_MOD_CONF_CTRL_0_OFFSET)
//#define CONFIGURATION_MOD_CONF_CTRL_0_RESERVED_POS 22
//#define CONFIGURATION_MOD_CONF_CTRL_0_RESERVED_NUMB 10
//#define CONFIGURATION_MOD_CONF_CTRL_0_RESERVED_RES_VAL 0x0
//R/W
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MCBSP1DIG_RF_CLKSEL_POS 20
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MCBSP1DIG_RF_CLKSEL_NUMB 2
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MCBSP1DIG_RF_CLKSEL_RES_VAL 0x0
//R/W
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MCBSP1_MOD_POS 19
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MCBSP1_MOD_NUMB 1
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MCBSP1_MOD_RES_VAL 0x0
//R/W
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MCBSP1_CLKS_SEL_R_POS 18
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MCBSP1_CLKS_SEL_R_NUMB 1
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MCBSP1_CLKS_SEL_R_RES_VAL 0x0
//R/W
#define CONFIGURATION_MOD_CONF_CTRL_0_MPU_NRST_CTL_POS 17
#define CONFIGURATION_MOD_CONF_CTRL_0_MPU_NRST_CTL_NUMB 1
#define CONFIGURATION_MOD_CONF_CTRL_0_MPU_NRST_CTL_RES_VAL 0x0
//R/W
//#define CONFIGURATION_MOD_CONF_CTRL_0_RESERVED_POS 16
//#define CONFIGURATION_MOD_CONF_CTRL_0_RESERVED_NUMB 1
//#define CONFIGURATION_MOD_CONF_CTRL_0_RESERVED_RES_VAL 0x0
//R/W
#define CONFIGURATION_MOD_CONF_CTRL_0_CAMERA_IF_POS 15
#define CONFIGURATION_MOD_CONF_CTRL_0_CAMERA_IF_NUMB 1
#define CONFIGURATION_MOD_CONF_CTRL_0_CAMERA_IF_RES_VAL 0x0
//R/W
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MCBSP1_CLK_SEL_R_POS 14
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MCBSP1_CLK_SEL_R_NUMB 1
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MCBSP1_CLK_SEL_R_RES_VAL 0x0
//R/W
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MMC2_CLK_SEL_R_POS 13
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MMC2_CLK_SEL_R_NUMB 1
#define CONFIGURATION_MOD_CONF_CTRL_0_CONF_MOD_MMC2_CLK_SEL_R_RES_VAL 0x0
//R/W
#define CONFIGURATION_MOD_CONF_CTRL_0_ISRAM_AUTO_IDLE_POS 12
#define CONFIGURATION_MOD_CONF_CTRL_0_ISRAM_AUTO_IDLE_NUMB 1
#define CONFIGURATION_MOD_CONF_CTRL_0_ISRAM_AUTO_IDLE_RES_VAL 0x0
//R/W
//#define CONFIGURATION_MOD_CONF_CTRL_0_RESERVED_POS 0
//#define CONFIGURATION_MOD_CONF_CTRL_0_RESERVED_NUMB 12
//#define CONFIGURATION_MOD_CONF_CTRL_0_RESERVED_RES_VAL 0x0
//R/W
//CONFIGURATION_FUNC_MUX_DSP_DMA_A
//-------------------
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_DSP_DMA_A_OFFSET)
//#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_RESERVED_POS 30
//#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_RESERVED_NUMB 2
//#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_RESERVED_RES_VAL 0x0
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_06_POS 25
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_06_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_06_RES_VAL 0x05
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_05_POS 20
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_05_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_05_RES_VAL 0x04
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_04_POS 15
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_04_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_04_RES_VAL 0x03
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_03_POS 10
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_03_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_03_RES_VAL 0x02
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_02_POS 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_02_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_02_RES_VAL 0x01
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_01_POS 0
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_01_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_CONF_DSP_DMA_REQ_01_RES_VAL 0x00
//R/W
//CONFIGURATION_FUNC_MUX_DSP_DMA_B
//-------------------
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_DSP_DMA_B_OFFSET)
//#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_RESERVED_POS 30
//#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_RESERVED_NUMB 2
//#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_RESERVED_RES_VAL 0x0
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_12_POS 25
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_12_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_12_RES_VAL 0x0B
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_11_POS 20
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_11_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_11_RES_VAL 0x0A
//R/W
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_10_POS 15
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_10_NUMB 5
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_CONF_DSP_DMA_REQ_10_RES_VAL 0x09
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