📄 configuration.h
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :neptune_configuration.h
//
// Date of Module Modification:5/26/04
// Date of Generation :5/27/04
//
//
//========================================================================
#include "mapping.h"
#ifndef _CONFIGURATION__H
#define _CONFIGURATION__H
//BEGIN INC GENERATION
//--------------------------------------
#define CONFIGURATION_BASE_ADDR_ARM 0xFFFE1000 /* 0xFFFE1000 */
//Register Offset
//-------------------
#define CONFIGURATION_FUNC_MUX_CTRL_0_OFFSET 0x0000
#define CONFIGURATION_COMP_MODE_CTRL_0_OFFSET 0x000C
#define CONFIGURATION_SECCTRL_1_OFFSET 0x0010
#define CONFIGURATION_SECCTRL_2_OFFSET 0x0014
#define CONFIGURATION_SEC_TEST_CTRL_OFFSET 0x0018
#define CONFIGURATION_SEC_TAP_CTRL_OFFSET 0x001C
#define CONFIGURATION_SEC_EMU_CTRL_OFFSET 0x0020
#define CONFIGURATION_SEC_STATUS_OFFSET 0x0024
#define CONFIGURATION_SEC_ERROR_OFFSET 0x0028
#define CONFIGURATION_CONF_REV_OFFSET 0x0058
#define CONFIGURATION_VOLTAGE_CTRL_0_OFFSET 0x0060
#define CONFIGURATION_USB_TRANSCEIVER_CTRL_OFFSET 0x0064
#define CONFIGURATION_TEST_DBG_CTRL_0_OFFSET 0x0070
#define CONFIGURATION_MOD_CONF_CTRL_0_OFFSET 0x0080
#define CONFIGURATION_FUNC_MUX_DSP_DMA_A_OFFSET 0x00D0
#define CONFIGURATION_FUNC_MUX_DSP_DMA_B_OFFSET 0x00D4
#define CONFIGURATION_FUNC_MUX_DSP_DMA_C_OFFSET 0x00D8
#define CONFIGURATION_FUNC_MUX_DSP_DMA_D_OFFSET 0x00DC
#define CONFIGURATION_FUNC_MUX_ARM_DMA_A_OFFSET 0x00EC
#define CONFIGURATION_FUNC_MUX_ARM_DMA_B_OFFSET 0x00F0
#define CONFIGURATION_FUNC_MUX_ARM_DMA_C_OFFSET 0x00F4
#define CONFIGURATION_FUNC_MUX_ARM_DMA_D_OFFSET 0x00F8
#define CONFIGURATION_FUNC_MUX_ARM_DMA_E_OFFSET 0x00FC
#define CONFIGURATION_FUNC_MUX_ARM_DMA_F_OFFSET 0x0100
#define CONFIGURATION_FUNC_MUX_ARM_DMA_G_OFFSET 0x0104
#define CONFIGURATION_MOD_CONF_CTRL_1_OFFSET 0x0110
#define CONFIGURATION_CONF_STATUS_OFFSET 0x0130
#define CONFIGURATION_RESET_CONTROL_OFFSET 0x0140
#define CONFIGURATION_CONF_OCPI_CTRL_OFFSET 0x0150
#define CONFIGURATION_FUNC1_ARMPERGATE_CLK_OFFSET 0x154
#define CONFIGURATION_FUNC2_ARMPERGATE_CLK_OFFSET 0x158
#define CONFIGURATION_SPARE_REG_OFFSET 0x2C
#define CONFIGURATION_COMP_MODE_CTRL_0 REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_COMP_MODE_CTRL_0_OFFSET)
//CONFIGURATION_FUNC_MUX_CTRL_0
//-------------------
#define CONFIGURATION_FUNC_MUX_CTRL_0 REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_FUNC_MUX_CTRL_0_OFFSET)
//#define CONFIGURATION_FUNC_MUX_CTRL_0_RESERVED_POS 21
//#define CONFIGURATION_FUNC_MUX_CTRL_0_RESERVED_NUMB 11
//#define CONFIGURATION_FUNC_MUX_CTRL_0_RESERVED_RES_VAL 0x0
//R
#define CONFIGURATION_FUNC_MUX_CTRL_0_LRU_SEL_POS 20
#define CONFIGURATION_FUNC_MUX_CTRL_0_LRU_SEL_NUMB 1
#define CONFIGURATION_FUNC_MUX_CTRL_0_LRU_SEL_RES_VAL 0x0
//R/W
//#define CONFIGURATION_FUNC_MUX_CTRL_0_RESERVED_POS 0
//#define CONFIGURATION_FUNC_MUX_CTRL_0_RESERVED_NUMB 20
//#define CONFIGURATION_FUNC_MUX_CTRL_0_RESERVED_RES_VAL 0x00
//R
//CONFIGURATION_COMP_MODE_CTRL_0
//-------------------
#define CONFIGURATION_COMP_MODE_CTRL_0 REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_COMP_MODE_CTRL_0_OFFSET)
//#define CONFIGURATION_COMP_MODE_CTRL_0_RESERVED_POS 16
//#define CONFIGURATION_COMP_MODE_CTRL_0_RESERVED_NUMB 16
//#define CONFIGURATION_COMP_MODE_CTRL_0_RESERVED_RES_VAL 0x0000
//R
#define CONFIGURATION_COMP_MODE_CTRL_0_CONF_MUX_EN_R_POS 0
#define CONFIGURATION_COMP_MODE_CTRL_0_CONF_MUX_EN_R_NUMB 16
#define CONFIGURATION_COMP_MODE_CTRL_0_CONF_MUX_EN_R_RES_VAL 0x0000
//R/W
//CONFIGURATION_SECCTRL_1
//-------------------
#define CONFIGURATION_SECCTRL_1 REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_SECCTRL_1_OFFSET)
//#define CONFIGURATION_SECCTRL_1_RESERVED_POS 8
//#define CONFIGURATION_SECCTRL_1_RESERVED_NUMB 24
//#define CONFIGURATION_SECCTRL_1_RESERVED_RES_VAL 0x0
//R
#define CONFIGURATION_SECCTRL_1_TM_PROTECT_EN_POS 7
#define CONFIGURATION_SECCTRL_1_TM_PROTECT_EN_NUMB 1
#define CONFIGURATION_SECCTRL_1_TM_PROTECT_EN_RES_VAL 0x1
//R/W
#define CONFIGURATION_SECCTRL_1_SEC_MODE_INIT_DONE_POS 6
#define CONFIGURATION_SECCTRL_1_SEC_MODE_INIT_DONE_NUMB 1
#define CONFIGURATION_SECCTRL_1_SEC_MODE_INIT_DONE_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_1_RNG_NS_ENABLE_POS 5
#define CONFIGURATION_SECCTRL_1_RNG_NS_ENABLE_NUMB 1
#define CONFIGURATION_SECCTRL_1_RNG_NS_ENABLE_RES_VAL 0x1
//R/W
#define CONFIGURATION_SECCTRL_1_PKA_NS_ENABLE_POS 4
#define CONFIGURATION_SECCTRL_1_PKA_NS_ENABLE_NUMB 1
#define CONFIGURATION_SECCTRL_1_PKA_NS_ENABLE_RES_VAL 0x1
//R/W
#define CONFIGURATION_SECCTRL_1_AES_NS_ENABLE_POS 3
#define CONFIGURATION_SECCTRL_1_AES_NS_ENABLE_NUMB 1
#define CONFIGURATION_SECCTRL_1_AES_NS_ENABLE_RES_VAL 0x1
//R/W
#define CONFIGURATION_SECCTRL_1_DES_NS_ENABLE_POS 2
#define CONFIGURATION_SECCTRL_1_DES_NS_ENABLE_NUMB 1
#define CONFIGURATION_SECCTRL_1_DES_NS_ENABLE_RES_VAL 0x1
//R/W
#define CONFIGURATION_SECCTRL_1_SHA_NS_ENABLE_POS 1
#define CONFIGURATION_SECCTRL_1_SHA_NS_ENABLE_NUMB 1
#define CONFIGURATION_SECCTRL_1_SHA_NS_ENABLE_RES_VAL 0x1
//R/W
#define CONFIGURATION_SECCTRL_1_SEC_CTRL1_WR_DISABLE_POS 0
#define CONFIGURATION_SECCTRL_1_SEC_CTRL1_WR_DISABLE_NUMB 1
#define CONFIGURATION_SECCTRL_1_SEC_CTRL1_WR_DISABLE_RES_VAL 0x0
//R/W
//CONFIGURATION_SECCTRL_2
//-------------------
#define CONFIGURATION_SECCTRL_2 REG32(CONFIGURATION_BASE_ADDR_ARM+CONFIGURATION_SECCTRL_2_OFFSET)
//#define CONFIGURATION_SECCTRL_2_RESERVED_POS 30
//#define CONFIGURATION_SECCTRL_2_RESERVED_NUMB 2
//#define CONFIGURATION_SECCTRL_2_RESERVED_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_DSP_SARAM_SEC_ENABLE_POS 22
#define CONFIGURATION_SECCTRL_2_DSP_SARAM_SEC_ENABLE_NUMB 8
#define CONFIGURATION_SECCTRL_2_DSP_SARAM_SEC_ENABLE_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_DSP_DARAM_SEC_ENABLE_POS 12
#define CONFIGURATION_SECCTRL_2_DSP_DARAM_SEC_ENABLE_NUMB 10
#define CONFIGURATION_SECCTRL_2_DSP_DARAM_SEC_ENABLE_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_SECURE_ELCD_ENABLE_POS 11
#define CONFIGURATION_SECCTRL_2_SECURE_ELCD_ENABLE_NUMB 1
#define CONFIGURATION_SECCTRL_2_SECURE_ELCD_ENABLE_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_SECURE_ISRAM_ENABLE_POS 10
#define CONFIGURATION_SECCTRL_2_SECURE_ISRAM_ENABLE_NUMB 1
#define CONFIGURATION_SECCTRL_2_SECURE_ISRAM_ENABLE_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_ISRAM_ERASE_START_POS 9
#define CONFIGURATION_SECCTRL_2_ISRAM_ERASE_START_NUMB 1
#define CONFIGURATION_SECCTRL_2_ISRAM_ERASE_START_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_ISRAM_ERASE_DISABLE_POS 8
#define CONFIGURATION_SECCTRL_2_ISRAM_ERASE_DISABLE_NUMB 1
#define CONFIGURATION_SECCTRL_2_ISRAM_ERASE_DISABLE_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_SECRAM_ERASE_START_POS 7
#define CONFIGURATION_SECCTRL_2_SECRAM_ERASE_START_NUMB 1
#define CONFIGURATION_SECCTRL_2_SECRAM_ERASE_START_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_SECRAM_ERASE_DISABLE_POS 6
#define CONFIGURATION_SECCTRL_2_SECRAM_ERASE_DISABLE_NUMB 1
#define CONFIGURATION_SECCTRL_2_SECRAM_ERASE_DISABLE_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_SECRAM_EXEC_DISABLE_POS 5
#define CONFIGURATION_SECCTRL_2_SECRAM_EXEC_DISABLE_NUMB 1
#define CONFIGURATION_SECCTRL_2_SECRAM_EXEC_DISABLE_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_PAD_CONF_ACC_DISABLE_POS 4
#define CONFIGURATION_SECCTRL_2_PAD_CONF_ACC_DISABLE_NUMB 1
#define CONFIGURATION_SECCTRL_2_PAD_CONF_ACC_DISABLE_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_SEC_KEYS_ACC_ENABLE_POS 3
#define CONFIGURATION_SECCTRL_2_SEC_KEYS_ACC_ENABLE_NUMB 1
#define CONFIGURATION_SECCTRL_2_SEC_KEYS_ACC_ENABLE_RES_VAL 0x1
//R/W
#define CONFIGURATION_SECCTRL_2_WD_REG_ENABLE_POS 2
#define CONFIGURATION_SECCTRL_2_WD_REG_ENABLE_NUMB 1
#define CONFIGURATION_SECCTRL_2_WD_REG_ENABLE_RES_VAL 0x1
//R/W
#define CONFIGURATION_SECCTRL_2_WD_OP_DISABLE_POS 1
#define CONFIGURATION_SECCTRL_2_WD_OP_DISABLE_NUMB 1
#define CONFIGURATION_SECCTRL_2_WD_OP_DISABLE_RES_VAL 0x0
//R/W
#define CONFIGURATION_SECCTRL_2_SEC_CTRL2_WR_DISABLE_POS 0
#define CONFIGURATION_SECCTRL_2_SEC_CTRL2_WR_DISABLE_NUMB 1
#define CONFIGURATION_SECCTRL_2_SEC_CTRL2_WR_DISABLE_RES_VAL 0x0
//R/W
//CONFIGURATION_SEC_TEST_CTRL
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