vspi.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Filename             : vspi.h

   Description          : Header file for the Voice Serial Port Interface

   Project              : Perseus

   Author               : Vincent Bour

   FUNCTIONS PROVIDED	:
			  SPI_TestRegisters
			  SPI_InitSet1
			  SPI_InitSet2
			  SPI_InitCTRL
			  SPI_write_LSB
			  SPI_write_MSB
			  SPI_read_LSB
			  SPI_read_MSB
			  SPI_read_Status
			  SPI_IsReadEnd
			  SPI_IsWriteEnd
			  SPI_StartClock
			  SPI_StopClock

===============================================================================
*/

#ifndef _VSPI__HH
#define _VSPI__HH

// include files
#include "global_types.h"
#include "mapping.h"

// define registers mapping
#define VSPI_SET1_OFFSET   0x000
#define VSPI_SET2_OFFSET   0x002
#define VSPI_CTRL_OFFSET   0x004
#define VSPI_STATUS_OFFSET 0x006
#define VSPI_TX_LSB_OFFSET 0x008
#define VSPI_TX_MSB_OFFSET 0x00A
#define VSPI_RX_LSB_OFFSET 0x00C
#define VSPI_RX_MSB_OFFSET 0x00E

#define VSPI_SET1_ADDR   (VSPI_BASE_ADDR + VSPI_SET1_OFFSET)
#define VSPI_SET2_ADDR   (VSPI_BASE_ADDR + VSPI_SET2_OFFSET)
#define VSPI_CTRL_ADDR   (VSPI_BASE_ADDR + VSPI_CTRL_OFFSET)
#define VSPI_STATUS_ADDR (VSPI_BASE_ADDR + VSPI_STATUS_OFFSET)
#define VSPI_TX_LSB_ADDR (VSPI_BASE_ADDR + VSPI_TX_LSB_OFFSET)
#define VSPI_TX_MSB_ADDR (VSPI_BASE_ADDR + VSPI_TX_MSB_OFFSET)
#define VSPI_RX_LSB_ADDR (VSPI_BASE_ADDR + VSPI_RX_LSB_OFFSET)
#define VSPI_RX_MSB_ADDR (VSPI_BASE_ADDR + VSPI_RX_MSB_OFFSET)

// define mask register
#define VSPI_SET1_REG_MASK          0x003F
#define VSPI_SET1_EN_CLK_MASK       0x0001
#define VSPI_SET1_REG_RESET_VALUE   0x0030

#define VSPI_SET2_REG_MASK          0x7fff
#define VSPI_SET2_REG_RESET_VALUE   0x0000

#define VSPI_CTRL_REG_MASK          0x07ff
#define VSPI_CTRL_REG_RESET_VALUE   0x0000

#define VSPI_STATUS_REG_MASK        0x0007
#define VSPI_STATUS_RE_MASK         0x0001
#define VSPI_STATUS_WE_MASK         0x0002
#define VSPI_STATUS_REG_RESET_VALUE 0x0004
#define VSPI_STATUS_BUSY_VALUE      0x00

#define VSPI_TX_LSB_REG_RESET_VALUE 0x0000
#define VSPI_TX_MSB_REG_RESET_VALUE 0x0000

#define VSPI_RX_LSB_REG_RESET_VALUE 0x0000
#define VSPI_RX_MSB_REG_RESET_VALUE 0x0000

// define position bit fields
#define VSPI_SET1_PTV_POSBIT   1
#define VSPI_SET1_MSK0_POSBIT  4
#define VSPI_SET1_MSK1_POSBIT  5

#define VSPI_SET2_P_POSBIT     5
#define VSPI_SET2_L_POSBIT    10

#define VSPI_CTRL_WR_POSBIT    1
#define VSPI_CTRL_NB_POSBIT    2
#define VSPI_CTRL_AD_POSBIT    7
#define VSPI_DMA_EN_POSBIT    10


// define types
typedef enum
{
  VSPI_READ_ACTION,
  VSPI_WRITE_ACTION
} VSPI_Action_t;

typedef void (*VSPI_END) (VSPI_Action_t Action);

typedef enum
{
  VSPI_SET1_REG_RESET_ERROR = 3,
  VSPI_SET2_REG_RESET_ERROR,
  VSPI_CTRL_REG_RESET_ERROR,
  VSPI_STATUS_REG_RESET_ERROR,
  VSPI_TX_LSB_REG_RESET_ERROR,
  VSPI_TX_MSB_REG_RESET_ERROR,
  VSPI_RX_LSB_REG_RESET_ERROR,
  VSPI_RX_MSB_REG_RESET_ERROR,

  VSPI_SET1_REG_ACCESS_ERROR,
  VSPI_SET2_REG_ACCESS_ERROR,
  VSPI_CTRL_REG_ACCESS_ERROR,

  VSPI_TX_LSB_REG_ACCESS_ERROR,
  VSPI_TX_MSB_REG_ACCESS_ERROR
} VSPI_Error_t;

//Clock Enable toggle
typedef enum
{
  VSPI_SHUT_OFF_CLOCK = 0,
  VSPI_RUN_CLOCK      = 1
} VSPI_EnableClock_t;

//Pres-scale clock divisor
typedef enum
{
  VSPI_SET1_PTV1  = 0,
  VSPI_SET1_PTV2  = 1,
  VSPI_SET1_PTV4  = 2,
  VSPI_SET1_PTV8  = 3,
  VSPI_SET1_PTV16 = 4
} VSPI_Ptv_t;

//Enable Interrupt for Write Cycle
typedef enum
{
  VSPI_ENABLE_IT_WRITE  = 0,
  VSPI_DISABLE_IT_WRITE = 1
} VSPI_MaskIntWr_t;

//Enable Interrupt for Read/Write Cycle
typedef enum
{
  VSPI_ENABLE_IT_READWRITE  = 0,
  VSPI_DISABLE_IT_READWRITE = 1
} VSPI_MaskIntRdWr_t;

typedef enum
{
  VSPI_DEV0_FALLING_EDGE_CLOCK = 0,
  VSPI_DEV1_FALLING_EDGE_CLOCK = 0,
  VSPI_DEV2_FALLING_EDGE_CLOCK = 0,
  VSPI_DEV3_FALLING_EDGE_CLOCK = 0,
  VSPI_DEV4_FALLING_EDGE_CLOCK = 0,

  VSPI_DEV0_RISING_EDGE_CLOCK  = 1,
  VSPI_DEV1_RISING_EDGE_CLOCK  = 2,
  VSPI_DEV2_RISING_EDGE_CLOCK  = 4,
  VSPI_DEV3_RISING_EDGE_CLOCK  = 8,
  VSPI_DEV4_RISING_EDGE_CLOCK  = 16
} VSPI_EdgeClock_t;

//Format of enable signals nTSPEN P(ositive)
typedef enum
{
  VSPI_DEV0_NEGATIVE_LEVEL_SIG = 0,
  VSPI_DEV1_NEGATIVE_LEVEL_SIG = 0,
  VSPI_DEV2_NEGATIVE_LEVEL_SIG = 0,
  VSPI_DEV3_NEGATIVE_LEVEL_SIG = 0,
  VSPI_DEV4_NEGATIVE_LEVEL_SIG = 0,

  VSPI_DEV0_POSITIVE_LEVEL_SIG = 1,
  VSPI_DEV1_POSITIVE_LEVEL_SIG = 2,
  VSPI_DEV2_POSITIVE_LEVEL_SIG = 4,
  VSPI_DEV3_POSITIVE_LEVEL_SIG = 8,
  VSPI_DEV4_POSITIVE_LEVEL_SIG = 16
} VSPI_Ptspen_t;

//Format of enable signals nTSPEN L(evel)
typedef enum
{
  VSPI_DEV0_LEVEL_TRIGGER_SIG = 0,
  VSPI_DEV1_LEVEL_TRIGGER_SIG = 0,
  VSPI_DEV2_LEVEL_TRIGGER_SIG = 0,
  VSPI_DEV3_LEVEL_TRIGGER_SIG = 0,
  VSPI_DEV4_LEVEL_TRIGGER_SIG = 0,

  VSPI_DEV0_EDGE_TRIGGER_SIG  = 1,
  VSPI_DEV1_EDGE_TRIGGER_SIG  = 2,
  VSPI_DEV2_EDGE_TRIGGER_SIG  = 4,
  VSPI_DEV3_EDGE_TRIGGER_SIG  = 8,
  VSPI_DEV4_EDGE_TRIGGER_SIG  = 16
} VSPI_Ltspen_t;

//Read and write process activation set 0 and 1
typedef enum
{
  VSPI_DEACTIV_RDWR_PROCESS = 0,
  VSPI_ACTIV_RDWR_PROCESS   = 1
} VSPI_CtrlRd_t;

//Write process activation set 0 and 1
typedef enum
{
  VSPI_DEACTIV_WR_PROCESS = 0,
  VSPI_ACTIV_WR_PROCESS   = 1
} VSPI_CtrlWr_t;

//Transmission Length  Word size (from 1 to 32 )
typedef enum
{
  VSPI_CTRL_NB_1  = 0x00, // One Bit Transmit
  VSPI_CTRL_NB_2,         // Two bits transmit
  VSPI_CTRL_NB_3,  VSPI_CTRL_NB_4,  VSPI_CTRL_NB_5,  VSPI_CTRL_NB_6,
  VSPI_CTRL_NB_7,  VSPI_CTRL_NB_8,  VSPI_CTRL_NB_9,  VSPI_CTRL_NB_10,
  VSPI_CTRL_NB_11, VSPI_CTRL_NB_12, VSPI_CTRL_NB_13, VSPI_CTRL_NB_14,
  VSPI_CTRL_NB_15, VSPI_CTRL_NB_16, VSPI_CTRL_NB_17, VSPI_CTRL_NB_18,