configuration.h.s

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

;*******************************************************************************
;*
;* Confidential
;* Copyright (C) 2001 ARM Ltd
;* All rights reserved
;*
;*		ARM926EJ Configuration
;*		======================
;*
;*	Origin: ARM926EJ Validation Suite
;*	Author: Jon Rijk 17/02/1999
;*         $Id: Configuration.rca 1.28 Fri Nov  2 16:00:43 2001 dbrook Experimental $
;*
;*******************************************************************************
		

		GET	Configuration-Generic.h.s

		CONFIG_START

;*****************************************************************************
;		ARM926EJ
;*****************************************************************************

			[	TARGET = "ARM926EJ"
KNOWN_TARGET            SETL    {TRUE}

                        [       :LNOT: :DEF: ARM9ZFPGA
                        GBLL    ARM9ZFPGA
ARM9ZFPGA                       SETL    {FALSE}
                        ]

			GENERIC_CFG

DEVICE			CONFIG_SETS	"ARM9xx-S"
;DEVICE_ID		CONFIG_SETA	0x41069262
; Change made after consulation with Arnaud (ARM) on 12/17/01 to reflect ALPHA version of RTL
;DEVICE_ID		CONFIG_SETA	0x41069260
;Change made after consulation with Steve (ARM) on 01/10/2002 to reflect rev0.2 version of RTL
;DEVICE_ID		CONFIG_SETA	0x41069262
;Change made  on 03/16/2002 to reflect rev0.3 version of RTL
DEVICE_ID		CONFIG_SETA	0x41069263



; Architecture
ARM_ARCH                CONFIG_SETA    	5
VARIANT			CONFIG_SETS	"ARM9"
HARVARD                 CONFIG_SETL    	{TRUE}

SUPPORTS_26BIT          CONFIG_SETL    	{FALSE}
SUPPORTS_THUMB          CONFIG_SETL    	{TRUE}
SUPPORTS_ELSEGUNDO	CONFIG_SETL	{TRUE}
SUPPORTS_NON_STOP_DEBUG CONFIG_SETL     {TRUE}
COPROC_SUPPORT          CONFIG_SETL    	{TRUE}

COHERENT_ISTREAM        CONFIG_SETL    	{FALSE}
PC_FULL                 CONFIG_SETL    	{TRUE}
PC_BIT1SET              CONFIG_SETL    	{FALSE}
PC_OFFSET               CONFIG_SETA    	12
			
; Abort Handling
BASE_RESTORATION_SINGLE CONFIG_SETL    	{TRUE}
BASE_RESTORATION_MULTI  CONFIG_SETL    	{TRUE}
STM_WB_REG_IN_LIST	CONFIG_SETS	"Final Value"
LDM_ABT_REGS_UNDEFINED  CONFIG_SETL     {TRUE}          ; Architecturally undefined - aborted multiples may update the dest regs


; Coprocessor
CP_BUSY_WAIT            CONFIG_SETL    	{TRUE}
CP_BOUNCE               CP              p0
CP_DTL                  CP              p8

CONFIG_COPRO        	CONFIG_SETL	{FALSE}	; TRUE if testbench coprocessors have configurable features
CP_TRICKBOX_BW		CONFIG_SETA	1	; time CP_TRICKBOX busy waits for
CP_BUSYWAIT_BW		CONFIG_SETA	2	; time CP_BUSYWAIT busy waits for


; Interrupt
INTERRUPT_CONFIG        CONFIG_SETS    	"COPROC"
INTERRUPT_EXECUTE       CONFIG_SETL     {TRUE}		; set this to TRUE for a REV 1 ARM9E!!
INTERRUPT_NUMNOPS       CONFIG_SETA     6
INTERRUPT_XCYCLES       CONFIG_SETA     9
			[       INTERRUPT_EXECUTE
	; ARM9Er1 can interrupt an instruction in execute, by using
	; "CCFAIL". This means the interrupt can occur a cycle
	; earlier if asserted on the first cycle of an instruction,
	; requiring one less NOP.
INTERRUPT_NUMNOPS       CONFIG_SETA     INTERRUPT_NUMNOPS - 1
			]

; Debug support                 
DEBUG_DBGRQ             CONFIG_SETS     "CP_TRICKBOX"
DEBUG_VERSION           CONFIG_SETS     "6"

			
; Abort addresses
AbortStart              CONFIG_SETA  	0x40000000
BadAddress              CONFIG_SETA  	0x4F000000
NPabort                 CONFIG_SETA  	0x41000000
SWPabort                CONFIG_SETA 	0x42000000
AbortEnd                CONFIG_SETA 	0x50000000
SingleAbort             CONFIG_SETA 	0x50000020

BIG_ENDIAN_MEMSYS	CONFIG_SETL	{TRUE}		; memory system will switch as cp15 endian is changed.
			
; Memory mapped Peripherals
TOP_OF_MEMORY		CONFIG_SETA	0x08000000	; for C stack (top of DRAM) NB aliased
			
TB_BASE			CONFIG_SETA	0x13000000
TB_TUBE			CONFIG_SETA	TB_BASE + 0
TB_LOABORT		CONFIG_SETA	TB_BASE + 0x40
TB_HIABORT		CONFIG_SETA	TB_BASE + 0x44
TB_EDBGRQ		CONFIG_SETA	TB_BASE + 0x48
TB_EDBGRQReg		CONFIG_SETA	TB_BASE + 0x58
TB_SWIACCEL		CONFIG_SETA	TB_BASE + 0x60
TB_SINGLEABORT		CONFIG_SETA	TB_BASE + 0x64
TB_CYCLETIMER 		CONFIG_SETA	TB_BASE + 0x80
TB_DEMONSWI		CONFIG_SETA	TB_BASE + 0x280
TB_WATCHDOG		CONFIG_SETA	TB_BASE + 0x284

SUPPORTS_BYTE_SINGLEABORT CONFIG_SETL   {FALSE}
			
;redundant Trickbox variables that need to be removed sometime			
TrickBox_base           CONFIG_SETA 	TB_BASE
TubeAd                  CONFIG_SETA	TB_TUBE
LowAbortReg             CONFIG_SETA   	TB_LOABORT
HighAbortReg            CONFIG_SETA    	TB_HIABORT
SWIAccelAd              CONFIG_SETA	TB_SWIACCEL
CLibEmul                CONFIG_SETA	TB_DEMONSWI
WPTAdd                  CONFIG_SETA	0x1300004C

; Cache
HAS_CACHE		CONFIG_SETL 	{TRUE}
HAS_CACHES		CONFIG_SETL	{TRUE}
WRITE_BACK              CONFIG_SETL    	{TRUE}
WRITE_THRO		CONFIG_SETL	{TRUE}
LOCKDOWN                CONFIG_SETL    	{TRUE}
SUPPORTS_INV_IND	CONFIG_SETL	{TRUE}
SUPPORTS_INV_ID		CONFIG_SETL	{TRUE}
SUPPORTS_INV_VA		CONFIG_SETL	{TRUE}
SUPPORTS_CLEAN_VA	CONFIG_SETL	{TRUE}
CACHEABLE_SWPS		CONFIG_SETL	{TRUE}
WRITES_ALWAYS_UPDATE_CACHE CONFIG_SETL	{FALSE}
UNEXPECTED_HITS		CONFIG_SETL	{FALSE}
SEGMENT_ASSOCIATIVE	CONFIG_SETL	{TRUE}
CACHE_NUM_COLUMN	CONFIG_SETA	32
CACHE_LINE_BOUNDARY	CONFIG_SETA	32
CACHE_NUM_COLUMN_BITS	CONFIG_SETA	5
LOCKDOWN_BASE_MASK	CONFIG_SETA	0xF
LOCKDOWN_BASE_LSB	CONFIG_SETA	0x0
LOCKDOWN_LOCK_BIT	CONFIG_SETA	0x0
INV_IND_OP2		CONFIG_SETA	2
INV_VA_OP2		CONFIG_SETA	1
WBUFFER_SIZE		CONFIG_SETA	16
UNIFIED_PU		CONFIG_SETL	{TRUE}

;MMU
MM_TYPE                 CONFIG_SETS     "MMU"
LOCKING_TLB             CONFIG_SETL     {TRUE}
UNIFIED_TLB             CONFIG_SETL     {TRUE}
;TTB_BASE		CONFIG_SETA	0xFFF80000
TTB_BASE		CONFIG_SETA	0xF0000000
TINY_PAGES		CONFIG_SETL	{TRUE}

;FAR
FAR_ALWAYS_UPDATES	CONFIG_SETL	{FALSE}

			]
 
;********************************************************************************
		
		CONFIG_END
		
;*****************************************************************************

;*****************************************************************************
		END