📄 msi2c_2.h
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#endif /* DSP_ACCESS */
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SCLH_16_0 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SCLH_OFFSET*coeff16_arm+0)
#else
#define MSI2C_2_I2C_SCLH_16_0 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_SCLH_OFFSET)
#endif
#define MSI2C_2_I2C_SCLH_16_0_RESERVED_POS 8
#define MSI2C_2_I2C_SCLH_16_0_RESERVED_NUMB 8
#define MSI2C_2_I2C_SCLH_16_0_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SCLH_16_0_SCLH_POS 0
#define MSI2C_2_I2C_SCLH_16_0_SCLH_NUMB 8
#define MSI2C_2_I2C_SCLH_16_0_SCLH_RES_VAL 0x0
//R/W
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SCLH_16_2 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SCLH_OFFSET*coeff16_arm+2)
#else
#define MSI2C_2_I2C_SCLH_16_2 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_SCLH_OFFSET+1)
#endif
#define MSI2C_2_I2C_SCLH_16_2_RESERVED_POS 8
#define MSI2C_2_I2C_SCLH_16_2_RESERVED_NUMB 8
#define MSI2C_2_I2C_SCLH_16_2_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SCLH_16_2_SCLH_POS 0
#define MSI2C_2_I2C_SCLH_16_2_SCLH_NUMB 8
#define MSI2C_2_I2C_SCLH_16_2_SCLH_RES_VAL 0x0
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SCLH_32 REG32(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SCLH_OFFSET*coeff32_arm)
#define MSI2C_2_I2C_SCLH_32_RESERVED_POS 8
#define MSI2C_2_I2C_SCLH_32_RESERVED_NUMB 8
#define MSI2C_2_I2C_SCLH_32_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SCLH_32_SCLH_POS 0
#define MSI2C_2_I2C_SCLH_32_SCLH_NUMB 8
#define MSI2C_2_I2C_SCLH_32_SCLH_RES_VAL 0x0
//R/W
//MSI2C_2_I2C_SYSTEST
#endif /* DSP_ACCESS */
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SYSTEST_16_0 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SYSTEST_OFFSET*coeff16_arm+0)
#else
#define MSI2C_2_I2C_SYSTEST_16_0 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_SYSTEST_OFFSET)
#endif
#define MSI2C_2_I2C_SYSTEST_16_0_ST_EN_POS 15
#define MSI2C_2_I2C_SYSTEST_16_0_ST_EN_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_0_ST_EN_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_16_0_FREE_POS 14
#define MSI2C_2_I2C_SYSTEST_16_0_FREE_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_0_FREE_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_16_0_TMODE_POS 12
#define MSI2C_2_I2C_SYSTEST_16_0_TMODE_NUMB 2
#define MSI2C_2_I2C_SYSTEST_16_0_TMODE_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_16_0_SSB_POS 11
#define MSI2C_2_I2C_SYSTEST_16_0_SSB_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_0_SSB_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_16_0_RESERVED_POS 4
#define MSI2C_2_I2C_SYSTEST_16_0_RESERVED_NUMB 7
#define MSI2C_2_I2C_SYSTEST_16_0_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SYSTEST_16_0_SCL_I_POS 3
#define MSI2C_2_I2C_SYSTEST_16_0_SCL_I_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_0_SCL_I_RES_VAL 0x0
//R
#define MSI2C_2_I2C_SYSTEST_16_0_SCL_O_POS 2
#define MSI2C_2_I2C_SYSTEST_16_0_SCL_O_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_0_SCL_O_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_16_0_SDA_I_POS 1
#define MSI2C_2_I2C_SYSTEST_16_0_SDA_I_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_0_SDA_I_RES_VAL 0x0
//R
#define MSI2C_2_I2C_SYSTEST_16_0_SDA_O_POS 0
#define MSI2C_2_I2C_SYSTEST_16_0_SDA_O_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_0_SDA_O_RES_VAL 0x0
//R/W
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SYSTEST_16_2 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SYSTEST_OFFSET*coeff16_arm+2)
#else
#define MSI2C_2_I2C_SYSTEST_16_2 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_SYSTEST_OFFSET+1)
#endif
#define MSI2C_2_I2C_SYSTEST_16_2_ST_EN_POS 15
#define MSI2C_2_I2C_SYSTEST_16_2_ST_EN_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_2_ST_EN_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_16_2_FREE_POS 14
#define MSI2C_2_I2C_SYSTEST_16_2_FREE_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_2_FREE_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_16_2_TMODE_POS 12
#define MSI2C_2_I2C_SYSTEST_16_2_TMODE_NUMB 2
#define MSI2C_2_I2C_SYSTEST_16_2_TMODE_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_16_2_SSB_POS 11
#define MSI2C_2_I2C_SYSTEST_16_2_SSB_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_2_SSB_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_16_2_RESERVED_POS 4
#define MSI2C_2_I2C_SYSTEST_16_2_RESERVED_NUMB 7
#define MSI2C_2_I2C_SYSTEST_16_2_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SYSTEST_16_2_SCL_I_POS 3
#define MSI2C_2_I2C_SYSTEST_16_2_SCL_I_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_2_SCL_I_RES_VAL 0x0
//R
#define MSI2C_2_I2C_SYSTEST_16_2_SCL_O_POS 2
#define MSI2C_2_I2C_SYSTEST_16_2_SCL_O_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_2_SCL_O_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_16_2_SDA_I_POS 1
#define MSI2C_2_I2C_SYSTEST_16_2_SDA_I_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_2_SDA_I_RES_VAL 0x0
//R
#define MSI2C_2_I2C_SYSTEST_16_2_SDA_O_POS 0
#define MSI2C_2_I2C_SYSTEST_16_2_SDA_O_NUMB 1
#define MSI2C_2_I2C_SYSTEST_16_2_SDA_O_RES_VAL 0x0
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SYSTEST_32 REG32(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SYSTEST_OFFSET*coeff32_arm)
#define MSI2C_2_I2C_SYSTEST_32_ST_EN_POS 15
#define MSI2C_2_I2C_SYSTEST_32_ST_EN_NUMB 1
#define MSI2C_2_I2C_SYSTEST_32_ST_EN_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_32_FREE_POS 14
#define MSI2C_2_I2C_SYSTEST_32_FREE_NUMB 1
#define MSI2C_2_I2C_SYSTEST_32_FREE_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_32_TMODE_POS 12
#define MSI2C_2_I2C_SYSTEST_32_TMODE_NUMB 2
#define MSI2C_2_I2C_SYSTEST_32_TMODE_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_32_SSB_POS 11
#define MSI2C_2_I2C_SYSTEST_32_SSB_NUMB 1
#define MSI2C_2_I2C_SYSTEST_32_SSB_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_SYSTEST_32_RESERVED_POS 4
#define MSI2C_2_I2C_SYSTEST_32_RESERVED_NUMB 7
#define MSI2C_2_I2C_SYSTEST_32_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SYSTEST_32_SCL_I_POS 3
#define MSI2C_2_I2C_SYSTEST_32_SCL_I_NUMB 1
#define MSI2C_2_I2C_SYSTEST_32_SCL_I_RES_VAL 0x0
//R
#define MSI2C_2_I2C_SYSTEST_32_SCL_O_POS 2
#define MSI2C_2_I2C_SYSTEST_32_SCL_O_NUMB 1
#define MSI2C_2_I2C_SYSTEST⌨️ 快捷键说明
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