📄 msi2c_2.h
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#ifndef DSP_ACCESS
#define MSI2C_2_I2C_OA_16_2 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_OA_OFFSET*coeff16_arm+2)
#else
#define MSI2C_2_I2C_OA_16_2 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_OA_OFFSET+1)
#endif
#define MSI2C_2_I2C_OA_16_2_RESERVED_POS 10
#define MSI2C_2_I2C_OA_16_2_RESERVED_NUMB 6
#define MSI2C_2_I2C_OA_16_2_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_OA_16_2_OA_POS 0
#define MSI2C_2_I2C_OA_16_2_OA_NUMB 10
#define MSI2C_2_I2C_OA_16_2_OA_RES_VAL 0x0
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_OA_32 REG32(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_OA_OFFSET*coeff32_arm)
#define MSI2C_2_I2C_OA_32_RESERVED_POS 10
#define MSI2C_2_I2C_OA_32_RESERVED_NUMB 6
#define MSI2C_2_I2C_OA_32_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_OA_32_OA_POS 0
#define MSI2C_2_I2C_OA_32_OA_NUMB 10
#define MSI2C_2_I2C_OA_32_OA_RES_VAL 0x0
//R/W
//MSI2C_2_I2C_SA
#endif /* DSP_ACCESS */
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SA_16_0 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SA_OFFSET*coeff16_arm+0)
#else
#define MSI2C_2_I2C_SA_16_0 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_SA_OFFSET)
#endif
#define MSI2C_2_I2C_SA_16_0_RESERVED_POS 10
#define MSI2C_2_I2C_SA_16_0_RESERVED_NUMB 6
#define MSI2C_2_I2C_SA_16_0_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SA_16_0_SA_POS 0
#define MSI2C_2_I2C_SA_16_0_SA_NUMB 10
#define MSI2C_2_I2C_SA_16_0_SA_RES_VAL 0x3FF
//R/W
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SA_16_2 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SA_OFFSET*coeff16_arm+2)
#else
#define MSI2C_2_I2C_SA_16_2 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_SA_OFFSET+1)
#endif
#define MSI2C_2_I2C_SA_16_2_RESERVED_POS 10
#define MSI2C_2_I2C_SA_16_2_RESERVED_NUMB 6
#define MSI2C_2_I2C_SA_16_2_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SA_16_2_SA_POS 0
#define MSI2C_2_I2C_SA_16_2_SA_NUMB 10
#define MSI2C_2_I2C_SA_16_2_SA_RES_VAL 0x3FF
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SA_32 REG32(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SA_OFFSET*coeff32_arm)
#define MSI2C_2_I2C_SA_32_RESERVED_POS 10
#define MSI2C_2_I2C_SA_32_RESERVED_NUMB 6
#define MSI2C_2_I2C_SA_32_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SA_32_SA_POS 0
#define MSI2C_2_I2C_SA_32_SA_NUMB 10
#define MSI2C_2_I2C_SA_32_SA_RES_VAL 0x3FF
//R/W
//MSI2C_2_I2C_PSC
#endif /* DSP_ACCESS */
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_PSC_16_0 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_PSC_OFFSET*coeff16_arm+0)
#else
#define MSI2C_2_I2C_PSC_16_0 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_PSC_OFFSET)
#endif
#define MSI2C_2_I2C_PSC_16_0_RESERVED_POS 8
#define MSI2C_2_I2C_PSC_16_0_RESERVED_NUMB 8
#define MSI2C_2_I2C_PSC_16_0_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_PSC_16_0_PSC_POS 0
#define MSI2C_2_I2C_PSC_16_0_PSC_NUMB 8
#define MSI2C_2_I2C_PSC_16_0_PSC_RES_VAL 0x0
//R/W
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_PSC_16_2 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_PSC_OFFSET*coeff16_arm+2)
#else
#define MSI2C_2_I2C_PSC_16_2 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_PSC_OFFSET+1)
#endif
#define MSI2C_2_I2C_PSC_16_2_RESERVED_POS 8
#define MSI2C_2_I2C_PSC_16_2_RESERVED_NUMB 8
#define MSI2C_2_I2C_PSC_16_2_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_PSC_16_2_PSC_POS 0
#define MSI2C_2_I2C_PSC_16_2_PSC_NUMB 8
#define MSI2C_2_I2C_PSC_16_2_PSC_RES_VAL 0x0
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_PSC_32 REG32(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_PSC_OFFSET*coeff32_arm)
#define MSI2C_2_I2C_PSC_32_RESERVED_POS 8
#define MSI2C_2_I2C_PSC_32_RESERVED_NUMB 8
#define MSI2C_2_I2C_PSC_32_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_PSC_32_PSC_POS 0
#define MSI2C_2_I2C_PSC_32_PSC_NUMB 8
#define MSI2C_2_I2C_PSC_32_PSC_RES_VAL 0x0
//R/W
//MSI2C_2_I2C_SCLL
#endif /* DSP_ACCESS */
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SCLL_16_0 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SCLL_OFFSET*coeff16_arm+0)
#else
#define MSI2C_2_I2C_SCLL_16_0 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_SCLL_OFFSET)
#endif
#define MSI2C_2_I2C_SCLL_16_0_RESERVED_POS 8
#define MSI2C_2_I2C_SCLL_16_0_RESERVED_NUMB 8
#define MSI2C_2_I2C_SCLL_16_0_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SCLL_16_0_SCLL_POS 0
#define MSI2C_2_I2C_SCLL_16_0_SCLL_NUMB 8
#define MSI2C_2_I2C_SCLL_16_0_SCLL_RES_VAL 0x0
//R/W
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SCLL_16_2 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SCLL_OFFSET*coeff16_arm+2)
#else
#define MSI2C_2_I2C_SCLL_16_2 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_SCLL_OFFSET+1)
#endif
#define MSI2C_2_I2C_SCLL_16_2_RESERVED_POS 8
#define MSI2C_2_I2C_SCLL_16_2_RESERVED_NUMB 8
#define MSI2C_2_I2C_SCLL_16_2_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SCLL_16_2_SCLL_POS 0
#define MSI2C_2_I2C_SCLL_16_2_SCLL_NUMB 8
#define MSI2C_2_I2C_SCLL_16_2_SCLL_RES_VAL 0x0
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SCLL_32 REG32(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SCLL_OFFSET*coeff32_arm)
#define MSI2C_2_I2C_SCLL_32_RESERVED_POS 8
#define MSI2C_2_I2C_SCLL_32_RESERVED_NUMB 8
#define MSI2C_2_I2C_SCLL_32_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SCLL_32_SCLL_POS 0
#define MSI2C_2_I2C_SCLL_32_SCLL_NUMB 8
#define MSI2C_2_I2C_SCLL_32_SCLL_RES_VAL 0x0
//R/W
//MSI2C_2_I2C_SCLH
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