📄 msi2c_2.h
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/*Header modified by DSP-CONVERT V1.01 Script on Tue Aug 13 14:51:43 MEST 2002*/
//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :msi2c.h
//
// Date of Module Modification:5/16/02
// Date of Generation :6/3/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _MSI2C_2__H
#define _MSI2C_2__H
//BEGIN INC GENERATION
//--------------------------------------
#ifndef DSP_ADJUST /* If DSP_ADJUST is not defined, we are using */
#define DSP_ADJUST /* include file for ARM code, we do not need any */
#endif /* modifications. If this file is used for DSP code, */
//Register Offset
//-------------------
#define coeff8_arm 1
#define coeff16_arm 1
#define coeff32_arm 1
//-------------------
#define MSI2C_2_I2C_REV_OFFSET (0x0 DSP_ADJUST)
#define MSI2C_2_I2C_SYSS_OFFSET (0x10 DSP_ADJUST)
#define MSI2C_2_I2C_BUF_OFFSET (0x14 DSP_ADJUST)
#define MSI2C_2_I2C_CNT_OFFSET (0x18 DSP_ADJUST)
#define MSI2C_2_I2C_DATA_OFFSET (0x1C DSP_ADJUST)
#define MSI2C_2_I2C_SYSC_OFFSET (0x20 DSP_ADJUST)
#define MSI2C_2_I2C_CON_OFFSET (0x24 DSP_ADJUST)
#define MSI2C_2_I2C_OA_OFFSET (0x28 DSP_ADJUST)
#define MSI2C_2_I2C_SA_OFFSET (0x2C DSP_ADJUST)
#define MSI2C_2_I2C_PSC_OFFSET (0x30 DSP_ADJUST)
#define MSI2C_2_I2C_SCLL_OFFSET (0x34 DSP_ADJUST)
#define MSI2C_2_I2C_SCLH_OFFSET (0x38 DSP_ADJUST)
#define MSI2C_2_I2C_SYSTEST_OFFSET (0x3C DSP_ADJUST)
#define MSI2C_2_I2C_IE_OFFSET (0x4 DSP_ADJUST)
#define MSI2C_2_I2C_STAT_OFFSET (0x8 DSP_ADJUST)
#ifndef DSP_ACCESS
//MSI2C_2_I2C_REV
#endif /* DSP_ACCESS */
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_REV_16_0 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_REV_OFFSET*coeff16_arm+0)
#else
#define MSI2C_2_I2C_REV_16_0 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_REV_OFFSET)
#endif
#define MSI2C_2_I2C_REV_16_0_RESERVED_POS 8
#define MSI2C_2_I2C_REV_16_0_RESERVED_NUMB 8
#define MSI2C_2_I2C_REV_16_0_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_REV_16_0_REV_POS 0
#define MSI2C_2_I2C_REV_16_0_REV_NUMB 8
#define MSI2C_2_I2C_REV_16_0_REV_RES_VAL 0x34
//R
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_REV_16_2 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_REV_OFFSET*coeff16_arm+2)
#else
#define MSI2C_2_I2C_REV_16_2 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_REV_OFFSET+1)
#endif
#define MSI2C_2_I2C_REV_16_2_RESERVED_POS 8
#define MSI2C_2_I2C_REV_16_2_RESERVED_NUMB 8
#define MSI2C_2_I2C_REV_16_2_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_REV_16_2_REV_POS 0
#define MSI2C_2_I2C_REV_16_2_REV_NUMB 8
#define MSI2C_2_I2C_REV_16_2_REV_RES_VAL 0x34
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_REV_32 REG32(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_REV_OFFSET*coeff32_arm)
#define MSI2C_2_I2C_REV_32_RESERVED_POS 8
#define MSI2C_2_I2C_REV_32_RESERVED_NUMB 8
#define MSI2C_2_I2C_REV_32_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_REV_32_REV_POS 0
#define MSI2C_2_I2C_REV_32_REV_NUMB 8
#define MSI2C_2_I2C_REV_32_REV_RES_VAL 0x34
//R
//MSI2C_2_I2C_SYSS
#endif /* DSP_ACCESS */
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SYSS_16_0 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SYSS_OFFSET*coeff16_arm+0)
#else
#define MSI2C_2_I2C_SYSS_16_0 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_SYSS_OFFSET)
#endif
#define MSI2C_2_I2C_SYSS_16_0_RESERVED_POS 1
#define MSI2C_2_I2C_SYSS_16_0_RESERVED_NUMB 15
#define MSI2C_2_I2C_SYSS_16_0_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SYSS_16_0_RDONE_POS 0
#define MSI2C_2_I2C_SYSS_16_0_RDONE_NUMB 1
#define MSI2C_2_I2C_SYSS_16_0_RDONE_RES_VAL 0x0
//R
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SYSS_16_2 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SYSS_OFFSET*coeff16_arm+2)
#else
#define MSI2C_2_I2C_SYSS_16_2 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_SYSS_OFFSET+1)
#endif
#define MSI2C_2_I2C_SYSS_16_2_RESERVED_POS 1
#define MSI2C_2_I2C_SYSS_16_2_RESERVED_NUMB 15
#define MSI2C_2_I2C_SYSS_16_2_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SYSS_16_2_RDONE_POS 0
#define MSI2C_2_I2C_SYSS_16_2_RDONE_NUMB 1
#define MSI2C_2_I2C_SYSS_16_2_RDONE_RES_VAL 0x0
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_SYSS_32 REG32(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_SYSS_OFFSET*coeff32_arm)
#define MSI2C_2_I2C_SYSS_32_RESERVED_POS 1
#define MSI2C_2_I2C_SYSS_32_RESERVED_NUMB 15
#define MSI2C_2_I2C_SYSS_32_RESERVED_RES_VAL 0x0
//None
#define MSI2C_2_I2C_SYSS_32_RDONE_POS 0
#define MSI2C_2_I2C_SYSS_32_RDONE_NUMB 1
#define MSI2C_2_I2C_SYSS_32_RDONE_RES_VAL 0x0
//R
//MSI2C_2_I2C_BUF
#endif /* DSP_ACCESS */
#ifndef DSP_ACCESS
#define MSI2C_2_I2C_BUF_16_0 REG16(MSI2C_2_BASE_ADDR_ARM+MSI2C_2_I2C_BUF_OFFSET*coeff16_arm+0)
#else
#define MSI2C_2_I2C_BUF_16_0 REG16(MSI2C_2_BASE_ADDR_DSP+MSI2C_2_I2C_BUF_OFFSET)
#endif
#define MSI2C_2_I2C_BUF_16_0_RDMA_EN_POS 15
#define MSI2C_2_I2C_BUF_16_0_RDMA_EN_NUMB 1
#define MSI2C_2_I2C_BUF_16_0_RDMA_EN_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_BUF_16_0_RESERVED1_POS 8
#define MSI2C_2_I2C_BUF_16_0_RESERVED1_NUMB 7
#define MSI2C_2_I2C_BUF_16_0_RESERVED1_RES_VAL 0x0
//None
#define MSI2C_2_I2C_BUF_16_0_XDMA_EN_POS 7
#define MSI2C_2_I2C_BUF_16_0_XDMA_EN_NUMB 1
#define MSI2C_2_I2C_BUF_16_0_XDMA_EN_RES_VAL 0x0
//R/W
#define MSI2C_2_I2C_BUF_16_0_RESERVED2_POS 0
#define MSI2C_2_I2C_BUF_16_0_RESERVED2_NUMB 7
#define MSI2C_2_I2C_BUF_16_0_RESERVED2_RES_VAL 0x0
//None
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