dualmodetimer1.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define            DUALMODETIMER1_TCLR_32_CE_RES_VAL                                                                     0x0
//R/W

#define            DUALMODETIMER1_TCLR_32_PRE_POS                                                                        5
#define            DUALMODETIMER1_TCLR_32_PRE_NUMB                                                                       1
#define            DUALMODETIMER1_TCLR_32_PRE_RES_VAL                                                                    0x0
//R/W

#define            DUALMODETIMER1_TCLR_32_PTV_POS                                                                        2
#define            DUALMODETIMER1_TCLR_32_PTV_NUMB                                                                       3
#define            DUALMODETIMER1_TCLR_32_PTV_RES_VAL                                                                    0x0
//R/W

#define            DUALMODETIMER1_TCLR_32_AR_POS                                                                         1
#define            DUALMODETIMER1_TCLR_32_AR_NUMB                                                                        1
#define            DUALMODETIMER1_TCLR_32_AR_RES_VAL                                                                     0x0
//R/W

#define            DUALMODETIMER1_TCLR_32_ST_POS                                                                         0
#define            DUALMODETIMER1_TCLR_32_ST_NUMB                                                                        1
#define            DUALMODETIMER1_TCLR_32_ST_RES_VAL                                                                     0x0
//R/W


//DUALMODETIMER1_TCRR

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TCRR_16_0                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TCRR_OFFSET*coeff16_arm+0)
#else
#define            DUALMODETIMER1_TCRR_16_0                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TCRR_OFFSET)
#endif


#define            DUALMODETIMER1_TCRR_16_0_TIME_COUNTER_POS                                                             0
#define            DUALMODETIMER1_TCRR_16_0_TIME_COUNTER_NUMB                                                            32
#define            DUALMODETIMER1_TCRR_16_0_TIME_COUNTER_RES_VAL                                                         0x00000000
//R/W



#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TCRR_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TCRR_OFFSET*coeff16_arm+2)
#else
#define            DUALMODETIMER1_TCRR_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TCRR_OFFSET+1)
#endif


#define            DUALMODETIMER1_TCRR_16_2_TIME_COUNTER_POS                                                             0
#define            DUALMODETIMER1_TCRR_16_2_TIME_COUNTER_NUMB                                                            32
#define            DUALMODETIMER1_TCRR_16_2_TIME_COUNTER_RES_VAL                                                         0x00000000

#ifndef DSP_ACCESS

#define            DUALMODETIMER1_TCRR_32                                                                              REG32(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TCRR_OFFSET*coeff32_arm)


#define            DUALMODETIMER1_TCRR_32_TIME_COUNTER_POS                                                               0
#define            DUALMODETIMER1_TCRR_32_TIME_COUNTER_NUMB                                                              32
#define            DUALMODETIMER1_TCRR_32_TIME_COUNTER_RES_VAL                                                           0x00000000
//R/W


//DUALMODETIMER1_TLDR

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TLDR_16_0                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TLDR_OFFSET*coeff16_arm+0)
#else
#define            DUALMODETIMER1_TLDR_16_0                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TLDR_OFFSET)
#endif


#define            DUALMODETIMER1_TLDR_16_0_TIME_VALUE_POS                                                               0
#define            DUALMODETIMER1_TLDR_16_0_TIME_VALUE_NUMB                                                              32
#define            DUALMODETIMER1_TLDR_16_0_TIME_VALUE_RES_VAL                                                           0x00000000
//R/W



#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TLDR_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TLDR_OFFSET*coeff16_arm+2)
#else
#define            DUALMODETIMER1_TLDR_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TLDR_OFFSET+1)
#endif


#define            DUALMODETIMER1_TLDR_16_2_TIME_VALUE_POS                                                               0
#define            DUALMODETIMER1_TLDR_16_2_TIME_VALUE_NUMB                                                              32
#define            DUALMODETIMER1_TLDR_16_2_TIME_VALUE_RES_VAL                                                           0x00000000

#ifndef DSP_ACCESS

#define            DUALMODETIMER1_TLDR_32                                                                              REG32(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TLDR_OFFSET*coeff32_arm)


#define            DUALMODETIMER1_TLDR_32_TIME_VALUE_POS                                                                 0
#define            DUALMODETIMER1_TLDR_32_TIME_VALUE_NUMB                                                                32
#define            DUALMODETIMER1_TLDR_32_TIME_VALUE_RES_VAL                                                             0x00000000
//R/W


//DUALMODETIMER1_TTGR

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TTGR_16_0                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TTGR_OFFSET*coeff16_arm+0)
#else
#define            DUALMODETIMER1_TTGR_16_0                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TTGR_OFFSET)
#endif


#define            DUALMODETIMER1_TTGR_16_0_TTGR_VALUE_POS                                                               0
#define            DUALMODETIMER1_TTGR_16_0_TTGR_VALUE_NUMB                                                              32
#define            DUALMODETIMER1_TTGR_16_0_TTGR_VALUE_RES_VAL                                                           0xFFFFFFFF
//R/W



#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TTGR_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TTGR_OFFSET*coeff16_arm+2)
#else
#define            DUALMODETIMER1_TTGR_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TTGR_OFFSET+1)
#endif


#define            DUALMODETIMER1_TTGR_16_2_TTGR_VALUE_POS                                                               0
#define            DUALMODETIMER1_TTGR_16_2_TTGR_VALUE_NUMB                                                              32
#define            DUALMODETIMER1_TTGR_16_2_TTGR_VALUE_RES_VAL                                                           0xFFFFFFFF

#ifndef DSP_ACCESS

#define            DUALMODETIMER1_TTGR_32                                                                              REG32(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TTGR_OFFSET*coeff32_arm)


#define            DUALMODETIMER1_TTGR_32_TTGR_VALUE_POS                                                                 0
#define            DUALMODETIMER1_TTGR_32_TTGR_VALUE_NUMB                                                                32
#define            DUALMODETIMER1_TTGR_32_TTGR_VALUE_RES_VAL                                                             0xFFFFFFFF
//R/W


//DUALMODETIMER1_TWPS

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TWPS_16_0                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TWPS_OFFSET*coeff16_arm+0)
#else
#define            DUALMODETIMER1_TWPS_16_0                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TWPS_OFFSET)
#endif


#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TMAR_POS                                                              4
#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TMAR_NUMB                                                             1
#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TMAR_RES_VAL                                                          0x0
//R

#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TTGR_POS                                                              3
#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TTGR_NUMB                                                             1
#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TTGR_RES_VAL                                                          0x0
//R

#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TLDR_POS                                                              2
#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TLDR_NUMB                                                             1
#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TLDR_RES_VAL                                                          0x0
//R

#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TCRR_POS                                                              1
#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TCRR_NUMB                                                             1
#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TCRR_RES_VAL                                                          0x0
//R

#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TCLR_POS                                                              0
#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TCLR_NUMB                                                             1
#define            DUALMODETIMER1_TWPS_16_0_W_PEND_TCLR_RES_VAL                                                          0x0
//R



#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TWPS_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TWPS_OFFSET*coeff16_arm+2)
#else
#define            DUALMODETIMER1_TWPS_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TWPS_OFFSET+1)
#endif


#define            DUALMODETIMER1_TWPS_16_2_W_PEND_TMAR_POS                                                              4
#define            DUALMODETIMER1_TWPS_16_2_W_PEND_TMAR_NUMB                                                             1
#define            DUALMODETIMER1_TWPS_16_2_W_PEND_TMAR_RES_VAL                                                          0x0
//R