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📄 dualmodetimer1.h

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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#define            DUALMODETIMER1_TWER_16_0_TCAR_WUP_ENA_POS                                                             2
#define            DUALMODETIMER1_TWER_16_0_TCAR_WUP_ENA_NUMB                                                            1
#define            DUALMODETIMER1_TWER_16_0_TCAR_WUP_ENA_RES_VAL                                                         0x0
//R/W

#define            DUALMODETIMER1_TWER_16_0_OVF_WUP_ENA_POS                                                              1
#define            DUALMODETIMER1_TWER_16_0_OVF_WUP_ENA_NUMB                                                             1
#define            DUALMODETIMER1_TWER_16_0_OVF_WUP_ENA_RES_VAL                                                          0x0
//R/W

#define            DUALMODETIMER1_TWER_16_0_MAT_WUP_ENA_POS                                                              0
#define            DUALMODETIMER1_TWER_16_0_MAT_WUP_ENA_NUMB                                                             1
#define            DUALMODETIMER1_TWER_16_0_MAT_WUP_ENA_RES_VAL                                                          0x0
//R/W



#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TWER_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TWER_OFFSET*coeff16_arm+2)
#else
#define            DUALMODETIMER1_TWER_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TWER_OFFSET+1)
#endif


#define            DUALMODETIMER1_TWER_16_2_TCAR_WUP_ENA_POS                                                             2
#define            DUALMODETIMER1_TWER_16_2_TCAR_WUP_ENA_NUMB                                                            1
#define            DUALMODETIMER1_TWER_16_2_TCAR_WUP_ENA_RES_VAL                                                         0x0
//R/W

#define            DUALMODETIMER1_TWER_16_2_OVF_WUP_ENA_POS                                                              1
#define            DUALMODETIMER1_TWER_16_2_OVF_WUP_ENA_NUMB                                                             1
#define            DUALMODETIMER1_TWER_16_2_OVF_WUP_ENA_RES_VAL                                                          0x0
//R/W

#define            DUALMODETIMER1_TWER_16_2_MAT_WUP_ENA_POS                                                              0
#define            DUALMODETIMER1_TWER_16_2_MAT_WUP_ENA_NUMB                                                             1
#define            DUALMODETIMER1_TWER_16_2_MAT_WUP_ENA_RES_VAL                                                          0x0

#ifndef DSP_ACCESS

#define            DUALMODETIMER1_TWER_32                                                                              REG32(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TWER_OFFSET*coeff32_arm)


#define            DUALMODETIMER1_TWER_32_TCAR_WUP_ENA_POS                                                               2
#define            DUALMODETIMER1_TWER_32_TCAR_WUP_ENA_NUMB                                                              1
#define            DUALMODETIMER1_TWER_32_TCAR_WUP_ENA_RES_VAL                                                           0x0
//R/W

#define            DUALMODETIMER1_TWER_32_OVF_WUP_ENA_POS                                                                1
#define            DUALMODETIMER1_TWER_32_OVF_WUP_ENA_NUMB                                                               1
#define            DUALMODETIMER1_TWER_32_OVF_WUP_ENA_RES_VAL                                                            0x0
//R/W

#define            DUALMODETIMER1_TWER_32_MAT_WUP_ENA_POS                                                                0
#define            DUALMODETIMER1_TWER_32_MAT_WUP_ENA_NUMB                                                               1
#define            DUALMODETIMER1_TWER_32_MAT_WUP_ENA_RES_VAL                                                            0x0
//R/W


//DUALMODETIMER1_TCLR

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TCLR_16_0                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TCLR_OFFSET*coeff16_arm+0)
#else
#define            DUALMODETIMER1_TCLR_16_0                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TCLR_OFFSET)
#endif


#define            DUALMODETIMER1_TCLR_16_0_PT_POS                                                                       12
#define            DUALMODETIMER1_TCLR_16_0_PT_NUMB                                                                      1
#define            DUALMODETIMER1_TCLR_16_0_PT_RES_VAL                                                                   0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_0_TRG_POS                                                                      10
#define            DUALMODETIMER1_TCLR_16_0_TRG_NUMB                                                                     2
#define            DUALMODETIMER1_TCLR_16_0_TRG_RES_VAL                                                                  0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_0_TCM_POS                                                                      8
#define            DUALMODETIMER1_TCLR_16_0_TCM_NUMB                                                                     2
#define            DUALMODETIMER1_TCLR_16_0_TCM_RES_VAL                                                                  0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_0_SCPWM_POS                                                                    7
#define            DUALMODETIMER1_TCLR_16_0_SCPWM_NUMB                                                                   1
#define            DUALMODETIMER1_TCLR_16_0_SCPWM_RES_VAL                                                                0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_0_CE_POS                                                                       6
#define            DUALMODETIMER1_TCLR_16_0_CE_NUMB                                                                      1
#define            DUALMODETIMER1_TCLR_16_0_CE_RES_VAL                                                                   0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_0_PRE_POS                                                                      5
#define            DUALMODETIMER1_TCLR_16_0_PRE_NUMB                                                                     1
#define            DUALMODETIMER1_TCLR_16_0_PRE_RES_VAL                                                                  0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_0_PTV_POS                                                                      2
#define            DUALMODETIMER1_TCLR_16_0_PTV_NUMB                                                                     3
#define            DUALMODETIMER1_TCLR_16_0_PTV_RES_VAL                                                                  0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_0_AR_POS                                                                       1
#define            DUALMODETIMER1_TCLR_16_0_AR_NUMB                                                                      1
#define            DUALMODETIMER1_TCLR_16_0_AR_RES_VAL                                                                   0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_0_ST_POS                                                                       0
#define            DUALMODETIMER1_TCLR_16_0_ST_NUMB                                                                      1
#define            DUALMODETIMER1_TCLR_16_0_ST_RES_VAL                                                                   0x0
//R/W



#ifndef DSP_ACCESS
#define            DUALMODETIMER1_TCLR_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TCLR_OFFSET*coeff16_arm+2)
#else
#define            DUALMODETIMER1_TCLR_16_2                                                                            REG16(DUALMODETIMER1_BASE_ADDR_DSP+DUALMODETIMER1_TCLR_OFFSET+1)
#endif


#define            DUALMODETIMER1_TCLR_16_2_PT_POS                                                                       12
#define            DUALMODETIMER1_TCLR_16_2_PT_NUMB                                                                      1
#define            DUALMODETIMER1_TCLR_16_2_PT_RES_VAL                                                                   0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_2_TRG_POS                                                                      10
#define            DUALMODETIMER1_TCLR_16_2_TRG_NUMB                                                                     2
#define            DUALMODETIMER1_TCLR_16_2_TRG_RES_VAL                                                                  0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_2_TCM_POS                                                                      8
#define            DUALMODETIMER1_TCLR_16_2_TCM_NUMB                                                                     2
#define            DUALMODETIMER1_TCLR_16_2_TCM_RES_VAL                                                                  0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_2_SCPWM_POS                                                                    7
#define            DUALMODETIMER1_TCLR_16_2_SCPWM_NUMB                                                                   1
#define            DUALMODETIMER1_TCLR_16_2_SCPWM_RES_VAL                                                                0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_2_CE_POS                                                                       6
#define            DUALMODETIMER1_TCLR_16_2_CE_NUMB                                                                      1
#define            DUALMODETIMER1_TCLR_16_2_CE_RES_VAL                                                                   0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_2_PRE_POS                                                                      5
#define            DUALMODETIMER1_TCLR_16_2_PRE_NUMB                                                                     1
#define            DUALMODETIMER1_TCLR_16_2_PRE_RES_VAL                                                                  0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_2_PTV_POS                                                                      2
#define            DUALMODETIMER1_TCLR_16_2_PTV_NUMB                                                                     3
#define            DUALMODETIMER1_TCLR_16_2_PTV_RES_VAL                                                                  0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_2_AR_POS                                                                       1
#define            DUALMODETIMER1_TCLR_16_2_AR_NUMB                                                                      1
#define            DUALMODETIMER1_TCLR_16_2_AR_RES_VAL                                                                   0x0
//R/W

#define            DUALMODETIMER1_TCLR_16_2_ST_POS                                                                       0
#define            DUALMODETIMER1_TCLR_16_2_ST_NUMB                                                                      1
#define            DUALMODETIMER1_TCLR_16_2_ST_RES_VAL                                                                   0x0

#ifndef DSP_ACCESS

#define            DUALMODETIMER1_TCLR_32                                                                              REG32(DUALMODETIMER1_BASE_ADDR_ARM+DUALMODETIMER1_TCLR_OFFSET*coeff32_arm)


#define            DUALMODETIMER1_TCLR_32_PT_POS                                                                         12
#define            DUALMODETIMER1_TCLR_32_PT_NUMB                                                                        1
#define            DUALMODETIMER1_TCLR_32_PT_RES_VAL                                                                     0x0
//R/W

#define            DUALMODETIMER1_TCLR_32_TRG_POS                                                                        10
#define            DUALMODETIMER1_TCLR_32_TRG_NUMB                                                                       2
#define            DUALMODETIMER1_TCLR_32_TRG_RES_VAL                                                                    0x0
//R/W

#define            DUALMODETIMER1_TCLR_32_TCM_POS                                                                        8
#define            DUALMODETIMER1_TCLR_32_TCM_NUMB                                                                       2
#define            DUALMODETIMER1_TCLR_32_TCM_RES_VAL                                                                    0x0
//R/W

#define            DUALMODETIMER1_TCLR_32_SCPWM_POS                                                                      7
#define            DUALMODETIMER1_TCLR_32_SCPWM_NUMB                                                                     1
#define            DUALMODETIMER1_TCLR_32_SCPWM_RES_VAL                                                                  0x0
//R/W

#define            DUALMODETIMER1_TCLR_32_CE_POS                                                                         6
#define            DUALMODETIMER1_TCLR_32_CE_NUMB                                                                        1

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