📄 mapping.h
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/*
===============================================================================
TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
Property of Texas Instruments
For Unrestricted Internal Use Only
Unauthorized reproduction and/or distribution is strictly prohibited.
This product is protected under copyright law and trade secret law
as an unpublished work.
Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved.
Filename : mapping.h
Description : Header file defining perseus registers mapping
Project : Perseus ... Adapted for Helen, then for Neptune
Author : Sebastien Sabatier
Adapted for Helen by : Jean-Philippe Ulpiano
Adapted for Neptune by : Maxime Bouvat-Merlin
===============================================================================
*/
#ifndef _MAPPING__HH
#define _MAPPING__HH
#define ALIGNOrNotOn32Bits(ADDR) ((ADDR)<<1)
#define ALIGNOrNotOn32Bits_from8bits(ADDR) ((ADDR)<<2) //offset *4
#define PUBLIC_RHEA_STROBE_0 0xFFFB0000
#define PUBLIC_RHEA_STROBE_1 0xFFFC0000
#define PRIVATE_RHEA_STROBE_0 0xFFFD0000
#define PRIVATE_RHEA_STROBE_1 0xFFFE0000
#define OFFSET_CS0 0x0000
#define OFFSET_CS1 0x0800
#define OFFSET_CS2 0x1000
#define OFFSET_CS3 0x1800
#define OFFSET_CS4 0x2000
#define OFFSET_CS5 0x2800
#define OFFSET_CS6 0x3000
#define OFFSET_CS7 0x3800
#define OFFSET_CS8 0x4000
#define OFFSET_CS9 0x4800
#define OFFSET_CS10 0x5000
#define OFFSET_CS11 0x5800
#define OFFSET_CS12 0x6000
#define OFFSET_CS13 0x6800
#define OFFSET_CS14 0x7000
#define OFFSET_CS15 0x7800
#define OFFSET_CS16 0x8000
#define OFFSET_CS17 0x8800
#define OFFSET_CS18 0x9000
#define OFFSET_CS19 0x9800
#define OFFSET_CS20 0xA000
#define OFFSET_CS21 0xA800
#define OFFSET_CS22 0xB000
#define OFFSET_CS23 0xB800
#define OFFSET_CS24 0xC000
#define OFFSET_CS25 0xC800
#define OFFSET_CS26 0xD000
#define OFFSET_CS27 0xD800
#define OFFSET_CS28 0xE000
#define OFFSET_CS29 0xE800
#define OFFSET_CS30 0xF000
#define OFFSET_CS31 0xF800
//=========================
// ARM Public Strobe0
//=========================
#define UART_MODEM1_BASE_ADDR_ARM 0xFFFB0000 /* 0xFFFB0000 */
#define USB_OTG_CTRL_BASE_ADDR_ARM 0xFFFB0400 /* */
#define UART_MODEM2_BASE_ADDR_ARM 0xFFFB0800 /* 0xFFFB0800 */
#define SPI_BASE_ADDR_ARM 0xFFFB0C00 /* 0xFFFB0C00 */
#define ULPD_BASE_ADDR_ARM 0xFFFB1000 /* 0xFFFE0800 */
#define DUALMODETIMER1_BASE_ADDR_ARM 0xFFFB1400 /* 0xFFFB1400 */
#define MCBSP1_BASE_ADDR_ARM 0xFFFB1800
#define DUALMODETIMER2_BASE_ADDR_ARM 0xFFFB1C00 /* 0xFFFB1C00 */
#define MAP_MCSI2_ADDR 0xFFFB2000 //May be renamed to
#define MAP_MCSI1_ADDR 0xFFFB2800 //May be renamed to
#define UWIRE_BASE_ADDR_ARM 0xFFFB3000 /* */
#define MSI2C_1_BASE_ADDR_ARM 0xFFFB3800 /* */
#define MSI2C_2_BASE_ADDR_ARM 0xFFFB3C00 /* */
#define USB_OTG_W2FC_BASE_ADDR_ARM 0xFFFB4000 /* */
#define MAP_CYPHER_ADDR 0xFFFB4800 //May be renarmed
#define TPU_REG_BASE_ADDR_ARM 0xFFFB5000
#define TPU_RAM_BASE_ADDR_ARM 0xFFFB5800
#define MEM_PWT_ADDR 0xFFFB6000 // May be renamed
#define MAP_GEA_ADDR 0xFFFB6800 // May be renamed
#define DIGRF_IF_BASE_ADDR_ARM 0xFFFB7000
#define MCBSP_DIGITAL_RF_BASE_ADDR_ARM 0xFFFB7400
#define MMC_SDIO1_BASE_ADDR_ARM 0xFFFB7800 /* 0xFFFB7800 */
#define MMC_SDIO2_BASE_ADDR_ARM 0xFFFB7C00 /* 0xFFFB7C00 */
#define MS_SUPERVISOR_ADDR 0xFFFB8000 // May be renamed
#define MAP_USIM_ADDR 0xFFFB8800 // May be renamed
#define TIMER_32K_BASE_ADDR_ARM 0xFFFB9000 /* OS Timer */
#define UART_MODEM3_BASE_ADDR_ARM 0xFFFB9800 /* 0xFFFB9800 */
#define USB_OTG_HHC_BASE_ADDR_ARM 0xFFFBA000 /* */
#define FRAME_COUNTER_BASE_ADDR_ARM 0xFFFBAC00 /* */
#define TSP_REG_BASE_ADDR_ARM 0xFFFBB000 /* */
#define MPU_RHEASWITCH_BASE_ADD 0xFFFBB800
#define HDQ_1WIRE_BASE_ADDR_ARM 0xFFFBC000 /* */
#define SYNCTIMER_BASE_ADDR_ARM 0xFFFBC400 /* 0xFFFBC400 */
#define SSW_BASE_ADDR_ARM 0xFFFBC800
#define NDFLASH_BASE_ADDR_ARM 0xFFFBCC00 /* 0xFFFBCC00 */
#define LPG1_BASE_ADDR 0xFFFBD000 // May be renamed
#define LPG2_BASE_ADDR 0xFFFBD800 // May be renamed
#define MAP_KBD_BASE_ADDR 0xFFFBE000 // May be renamed
#define GPIO1_BASE_ADDR_ARM 0xFFFBE400 /* 0xFFFBE400 */
#define GPIO2_BASE_ADDR_ARM 0xFFFBEC00 /* 0xFFFBEC00 */
#define GIGACELL_MB_ASE_ADDR_ARM 0xFFFBF000 /* GigaCell mailBox */
// ARM Public Rhea Bridge old definitions (need to be suppress from lib)
#define MAP_UART_BT_REG 0xFFFB0000
//#define MPU_RHEASWITCH_UART_BT 0xFFFB0000
//#define MAP_UART_MOD_REG (PUBLIC_RHEA_STROBE_0+OFFSET_CS1)
#define MAP_UWIRE_REG 0xFFFB3000
#define MAP_I2C_REG 0xFFFB3800
#define MAP_USB_REG 0xFFFB4000
#define MMC_BASE_ADDR 0xFFFB7800
#define TIMER32_BASE_ADDR 0xFFFB9000
#define UART_IRDA_ADDR 0xFFFB9800
#define MEM_GPIO1_ADDR 0xFFFBE400
#define MEM_GPIO2_ADDR 0xFFFBEC00
//=========================
// ARM Public Strobe1
//=========================
#define MAILBOX_BASE_ADDR_ARM 0xFFFCF000 /* 0xFFFCF000 */
//=========================
// ARM Private Strobe1
//=========================
#define ARMINTH_L20_BASE_ADDR_ARM 0xFFFE0000 /* 0xFFFE0000 */
#define CONFIGURATION_BASE_ADDR_ARM 0xFFFE1000 /* 0xFFFE1000 */
#define IO_CONFIGURATION_BASE_ADDR_ARM 0xFFFE1000 /* 0xFFFE1000 */
#define SECCTRL_STATUS_BASE_ADDR_ARM 0xFFFE115C /* 0xFFFE115C */
#define DIE_ID_BASE_ADDR_ARM 0xFFFE1800 /* */
#define PRODUCTION_ID_BASE_ADDR_ARM 0xFFFE2000 /* */
#define LDCONV_BASE_ADDR_ARM 0xFFFE3000 /* */
#define BCM_BASE_ADDR_ARM 0xFFFE3800 /* */
#define DES3DES_BASE_ADDR_ARM 0xFFFE4000 /* 0xFFFE4000 */
#define SHA1MD5_BASE_ADDR_ARM 0xFFFE4800 /* 0xFFFE4800 */
#define RNG_BASE_ADDR_ARM 0xFFFE5000 /* 0xFFFE5000 */
#define NEPTUNE_JTAG_BASE_ADDR_ARM 0xFFFE5800 /* */
#define SERIAL_LCD_BASE_ADDR 0xFFFE6000 /* */
#define AES_BASE_ADDR_ARM 0xFFFE6800 /* */
#define PKA_RAM_BASE_ADDR 0xFFFE9000 /* */
#define PKA_REG_BASE_ADDR 0xFFFE8000 /* */
#define SECUREWATCHDOG_BASE_ADDR_ARM 0xFFFEA800 /* 0xFFFEA800 */
#define WATCHDOG32KHZ_BASE_ADDR_ARM 0xFFFEB000 /* 0xFFFEB000 */
#define SECURE_CONFIG_REG 0xFFFED480
#define INT_MASK_ADDR 0xFFFECBA0
// ARM Private Rhea Bridge old definitions....
//#define MPU_IO_ADDR (PRIVATE_RHEA_STROBE_0+OFFSET_CS2)
//#define MEM_EXT_INTH_USER_ADDR 0xFFFE0000
//#define MEM_EXT_INTH_SUPERVISOR_ADDR 0xFFFE0000
//#define ULPD_SUPERVISOR_ADDR 0xFFFE0800
//#define DIE_ID_BASE_ADDR 0xFFFE1800
//=========================
// DSP Periph Address thru MPU
//=========================
#define MPUI_BASE_ADDRESS_DSP 0xE1020000
#define MCBSP1_ADDR_DSP 0xE1011800
#define MCSI2_ADDR_DSP 0xE1012000
#define MCSI1_ADDR_DSP 0xE1012800
#define CIPHER_BASE_ADDR_DSP 0xE1014800 // Cipher A51/52/53
#define TPU_REG_BASE_ADDR_DSP 0xE1015000
#define TPU_RAM_BASE_ADDR_DSP 0xE1015800
#define GEA_BASE_ADDR_DSP 0xFFFB6800
#define RF_BASE_ADDR_DSP 0xE1017000 // Digital RF
#define USIM_BASE_ADDR_DSP 0xE1018800
#define TSP_BASE_ADDR_DSP 0xE101B000
#define RHEA_SWITCH_DSP 0xE101B800
//Ideally, should be renamed (taken from mem.h)
#define MEM_DSP_RHEA_ADDR 0xE1000000
#define MEM_DSP_GPIO_ADDR 0xE101E000
#define MEM_DSP_UART_ADDR 0xE101E800
#define MEM_DSP_MB_ADDR 0xE101F000
#define MEM_DSP_CLKM_ADDR 0xE1008000
#define MEM_DSP_DSPMMU_ADDR 0xE1008800
//=========================
// OCP addresses
//=========================
#define CAMERA_CORE_BASE_ADDR_ARM 0x35000000
#define ELCD_BASE_ADDR_ARM 0x35000800
//=========================
// FPGA addresse (THALASSA)
//=========================
#define FPGA_BASE_ADDR_ARM 0x08420000
#endif
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