omap_32_dpll2.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :omap_32_dpll2.h
//
//   Date of Module Modification:4/25/02
//   Date of Generation :5/3/02
//
//
//========================================================================
#include "omap_32_mapping.h"
#ifndef _DPLL2__H
#define _DPLL2__H

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define            DPLL2_DPLL2_CTL_REG_OFFSET                                                                          0x00




//DPLL2_DPLL2_CTL_REG
//-------------------
#define            DPLL2_DPLL2_CTL_REG                                                                                 REG16(DPLL2_BASE_ADDR_ARM+DPLL2_DPLL2_CTL_REG_OFFSET)


//R/W

#define            DPLL2_DPLL2_CTL_REG_IAI_POS                                                                           14
#define            DPLL2_DPLL2_CTL_REG_IAI_NUMB                                                                          1
#define            DPLL2_DPLL2_CTL_REG_IAI_RES_VAL                                                                       0x0
//R/W

#define            DPLL2_DPLL2_CTL_REG_IOB_POS                                                                           13
#define            DPLL2_DPLL2_CTL_REG_IOB_NUMB                                                                          1
#define            DPLL2_DPLL2_CTL_REG_IOB_RES_VAL                                                                       0x1
//R/W

#define            DPLL2_DPLL2_CTL_REG_TEST_POS                                                                          12
#define            DPLL2_DPLL2_CTL_REG_TEST_NUMB                                                                         1
#define            DPLL2_DPLL2_CTL_REG_TEST_RES_VAL                                                                      0x0
//R/W

#define            DPLL2_DPLL2_CTL_REG_PLL_MULT_POS                                                                      7
#define            DPLL2_DPLL2_CTL_REG_PLL_MULT_NUMB                                                                     5
#define            DPLL2_DPLL2_CTL_REG_PLL_MULT_RES_VAL                                                                  0x0
//R/W

#define            DPLL2_DPLL2_CTL_REG_PLL_DIV_POS                                                                       5
#define            DPLL2_DPLL2_CTL_REG_PLL_DIV_NUMB                                                                      2
#define            DPLL2_DPLL2_CTL_REG_PLL_DIV_RES_VAL                                                                   0x0
//R/W

#define            DPLL2_DPLL2_CTL_REG_PLL_ENABLE_POS                                                                    4
#define            DPLL2_DPLL2_CTL_REG_PLL_ENABLE_NUMB                                                                   1
#define            DPLL2_DPLL2_CTL_REG_PLL_ENABLE_RES_VAL                                                                0x0
//R/W

#define            DPLL2_DPLL2_CTL_REG_BYPASS_DIV_POS                                                                    2
#define            DPLL2_DPLL2_CTL_REG_BYPASS_DIV_NUMB                                                                   2
#define            DPLL2_DPLL2_CTL_REG_BYPASS_DIV_RES_VAL                                                                0x0
//R/W

#define            DPLL2_DPLL2_CTL_REG_BREAKLN_POS                                                                       1
#define            DPLL2_DPLL2_CTL_REG_BREAKLN_NUMB                                                                      1
#define            DPLL2_DPLL2_CTL_REG_BREAKLN_RES_VAL                                                                   0x0
//R

#define            DPLL2_DPLL2_CTL_REG_LOCK_POS                                                                          0
#define            DPLL2_DPLL2_CTL_REG_LOCK_NUMB                                                                         1
#define            DPLL2_DPLL2_CTL_REG_LOCK_RES_VAL                                                                      0x0
//R

#endif