📄 mapping.h~
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/*=============================================================================== TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION Property of Texas Instruments For Unrestricted Internal Use Only Unauthorized reproduction and/or distribution is strictly prohibited. This product is protected under copyright law and trade secret law as an unpublished work. Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved. Filename : mapping.h Description : Header file defining perseus registers mapping Project : Perseus ... Adapted for Helen Author : Sebastien Sabatier Adapted for Helen by : Jean-Philippe Ulpiano===============================================================================*/#ifndef _MAPPING__HH#define _MAPPING__HH#define ALIGNOrNotOn32Bits(ADDR) ((ADDR)<<1)#define ALIGNOrNotOn32Bits_from8bits(ADDR) ((ADDR)<<2) //offset *4#define PUBLIC_RHEA_STROBE_0 0xFFFB0000#define PUBLIC_RHEA_STROBE_1 0xFFFC0000#define PRIVATE_RHEA_STROBE_0 0xFFFD0000#define PRIVATE_RHEA_STROBE_1 0xFFFE0000#define OFFSET_CS0 0x0000#define OFFSET_CS1 0x0800#define OFFSET_CS2 0x1000#define OFFSET_CS3 0x1800#define OFFSET_CS4 0x2000#define OFFSET_CS5 0x2800#define OFFSET_CS6 0x3000#define OFFSET_CS7 0x3800#define OFFSET_CS8 0x4000#define OFFSET_CS9 0x4800#define OFFSET_CS10 0x5000#define OFFSET_CS11 0x5800#define OFFSET_CS12 0x6000#define OFFSET_CS13 0x6800#define OFFSET_CS14 0x7000#define OFFSET_CS15 0x7800#define OFFSET_CS16 0x8000#define OFFSET_CS17 0x8800#define OFFSET_CS18 0x9000#define OFFSET_CS19 0x9800#define OFFSET_CS20 0xA000#define OFFSET_CS21 0xA800#define OFFSET_CS22 0xB000#define OFFSET_CS23 0xB800#define OFFSET_CS24 0xC000#define OFFSET_CS25 0xC800#define OFFSET_CS26 0xD000#define OFFSET_CS27 0xD800#define OFFSET_CS28 0xE000#define OFFSET_CS29 0xE800#define OFFSET_CS30 0xF000#define OFFSET_CS31 0xF800// ARM Public Rhea Bridge//========================#define MAP_UART_BT_REG (PUBLIC_RHEA_STROBE_0+OFFSET_CS0)#define MPU_RHEASWITCH_UART_BT (PUBLIC_RHEA_STROBE_0+OFFSET_CS0)#define MAP_UART_MOD_REG (PUBLIC_RHEA_STROBE_0+OFFSET_CS1)#define MCBSP_ADDR (PUBLIC_RHEA_STROBE_0+OFFSET_CS2)#define MAP_UWIRE_REG (PUBLIC_RHEA_STROBE_0+OFFSET_CS6)#define MAP_I2C_REG (PUBLIC_RHEA_STROBE_0+OFFSET_CS7)#define MAP_USB_REG (PUBLIC_RHEA_STROBE_0+OFFSET_CS8)#define MAP_RTC_REG (PUBLIC_RHEA_STROBE_0+OFFSET_CS9)#define ARMIO_ADDR (PUBLIC_RHEA_STROBE_0+OFFSET_CS10)#define MAP_PWL_REG (PUBLIC_RHEA_STROBE_0+OFFSET_CS11)#define MEM_PWT_ADDR (PUBLIC_RHEA_STROBE_0+OFFSET_CS12)#define CAMIF_BASE_ADDRESS (PUBLIC_RHEA_STROBE_0+OFFSET_CS13)#define MMC_BASE_ADDR (PUBLIC_RHEA_STROBE_0+OFFSET_CS15)#define MS_SUPERVISOR_ADDR (PUBLIC_RHEA_STROBE_0+OFFSET_CS16)#define TIMER32_BASE_ADDR (PUBLIC_RHEA_STROBE_0+OFFSET_CS18)#define UART_IRDA_ADDR (PUBLIC_RHEA_STROBE_0+OFFSET_CS19)#define MPU_RHEASWITCH_BASE_ADD (PUBLIC_RHEA_STROBE_0+OFFSET_CS25)#define LED1_BASE_ADDR (PUBLIC_RHEA_STROBE_0+OFFSET_CS26)#define LED2_BASE_ADDR (PUBLIC_RHEA_STROBE_0+OFFSET_CS27)#define MAP_UART_EVAL_REG (PUBLIC_RHEA_STROBE_1+OFFSET_CS29)// ARM Private Rhea Bridge//=========================#define MPU_IO_ADDR (PRIVATE_RHEA_STROBE_0+OFFSET_CS2)#define ULPD_SUPERVISOR_ADDR (PRIVATE_RHEA_STROBE_1+OFFSET_CS1)#define MUX_BASE_ADDR (PRIVATE_RHEA_STROBE_1+OFFSET_CS2)#define DIE_ID_BASE_ADDR (PRIVATE_RHEA_STROBE_1+OFFSET_CS3)// MCBSP1 on the DSP side#define MCBSP1_ADDR 0xE1011800// MCBSP3 on the DSP side#define MCBSP3_ADDR 0xE1017000// MCSI1 (BT) on the DSP side#define MCSI1_ADDR 0xE1012800// MCSI2 (COM) on the DSP side#define MCSI2_ADDR 0xE1012000#define GEA_BASE_ADDR 0xE1016800/************************************************************************ HELEN2_MAPPING.H added************************************************************************//************************************************************************ OMAP1610 DEDICATED MODULES *************************************************************************/#define GDD_BASE_ADDR_ARM 0x30001000 /* 0x30001000 */#define SST_BASE_ADDR_ARM 0x30000000 /* 0x30000000 */#define SSR_BASE_ADDR_ARM 0x30000800 /* 0x30000800 */#define STI_BASE_ADDR_ARM 0xFFFEA000 /* 0xFFFEA000 */#define USB_OTG_W2FC_BASE_ADDR_ARM 0xFFFB4000 /* */#define USB_OTG_CTRL_BASE_ADDR_ARM 0xFFFB0400 /* */#define USB_OTG_HHC_BASE_ADDR_ARM 0xFFFBA000 /* *//************************************************************************ MPU/DSP DYNAMICALLY SHARED PERIPHERALS *************************************************************************/#define GPIO1_BASE_ADDR_ARM 0xFFFBE400 /* 0xFFFBE400 */#define GPIO2_BASE_ADDR_ARM 0xFFFBEC00 /* 0xFFFBEC00 */#define GPIO3_BASE_ADDR_ARM 0xFFFBB400 /* 0xFFFBB400 */#define GPIO4_BASE_ADDR_ARM 0xFFFBBC00 /* 0xFFFBBC00 */#define SYNCTIMER_BASE_ADDR_ARM 0xFFFBC400 /* 0xFFFBC400 *//************************************************************************ MPU SHARED PERIPHERALS *************************************************************************/#define HDQ_1WIRE_BASE_ADDR_ARM 0xFFFBC000 /* */#define UWIRE_BASE_ADDR_ARM 0xFFFB3000 /* */#define MMC_SDIO1_BASE_ADDR_ARM 0xFFFB7800 /* 0xFFFB7800 */#define ARMIO_BASE_ADDR_ARM 0xFFFB5000 /* 0xFFFB5000 */#define CAMERA_INTERFACE_BASE_ADDR_ARM 0x2007D800 /* 0xFFFB6800 */#define SOSSI_BASE_ADDR_ARM 0xFFFBAC00 /* 0xFFFBAC00 */#define CCP_BASE_ADDR_ARM 0x2007D000 /*0xFFFB8C00*/ /*0xFFFC7800*/ /* 0xFFFB8C00 */#define RTC_BASE_ADDR_ARM 0xFFFB4800 /* */#define FAC_BASE_ADDR_ARM 0xFFFBA800 /* */#define TIMER_32K_BASE_ADDR_ARM 0xFFFB9000 /* *//************************************************************************ MPU/DSP STATICALLY SHARED PERIPHERALS *************************************************************************/#define DUALMODETIMER1_BASE_ADDR_ARM 0xFFFB1400 /* 0xFFFB1400 */#define DUALMODETIMER2_BASE_ADDR_ARM 0xFFFB1C00 /* 0xFFFB1C00 */#define DUALMODETIMER3_BASE_ADDR_ARM 0xFFFB2400 /* 0xFFFB2400 */#define DUALMODETIMER4_BASE_ADDR_ARM 0xFFFB2C00 /* 0xFFFB2C00 */#define DUALMODETIMER5_BASE_ADDR_ARM 0xFFFB3400 /* 0xFFFB3400 */#define DUALMODETIMER6_BASE_ADDR_ARM 0xFFFB3C00 /* 0xFFFB3C00 */#define DUALMODETIMER7_BASE_ADDR_ARM 0xFFFB7400 /* 0xFFFB7400 */#define DUALMODETIMER8_BASE_ADDR_ARM 0xFFFBD400 /* 0xFFFB8400!! */#define SPI_BASE_ADDR_ARM 0xFFFB0C00 /* 0xFFFB0C00 */#define NDFLASH_BASE_ADDR_ARM 0xFFFBCC00 /* 0xFFFBCC00 */#define UART_MODEM1_BASE_ADDR_ARM 0xFFFB0000 /* 0xFFFB0000 */#define UART_MODEM2_BASE_ADDR_ARM 0xFFFB0800 /* 0xFFFB0800 */#define UART_MODEM3_BASE_ADDR_ARM 0xFFFB9800 /* 0xFFFB9800 */#define MSI2C_BASE_ADDR_ARM 0xFFFB3800 /* */#define MMC_SDIO2_BASE_ADDR_ARM 0xFFFB7C00 /* 0xFFFB7C00 */#define MCBSP2_BASE_ADDR_ARM 0xFFFB1000 /* 0xFFFB1000 *//************************************************************************ MPU PRIVATE PERIPHERALS *************************************************************************/#define ARMINTH_L20_BASE_ADDR_ARM 0xFFFE0000 /* 0xFFFE0000 */#define SECUREWATCHDOG_BASE_ADDR_ARM 0xFFFEA800 /* 0xFFFEA800 */#define CONFIGURATION_BASE_ADDR_ARM 0xFFFE1000 /* 0xFFFE1000 */#define RNG_BASE_ADDR_ARM 0xFFFE5000 /* 0xFFFE5000 */#define DES3DES_BASE_ADDR_ARM 0xFFFE4000 /* 0xFFFE4000 */#define WATCHDOG32KHZ_BASE_ADDR_ARM 0xFFFEB000 /* 0xFFFEB000 */#define SHA1MD5_BASE_ADDR_ARM 0xFFFE4800 /* 0xFFFE4800 */#define LDCONV_BASE_ADDR_ARM 0xFFFE3000 /* *//************************************************************************ TEST MODULES *************************************************************************/#define BCM_BASE_ADDR_ARM 0xFFFE3800 /* */#define DIE_ID_BASE_ADDR_ARM 0xFFFE3800 /* */#define OMAP1610_JTAG_BASE_ADDR_ARM 0xFFFE5800 /* */#define PRODUCTION_ID_BASE_ADDR_ARM 0xFFFE1800 /* */#define SECURITY_BASE_ADDR_ARM 0xFFFED400 /* *//************************************************************************ OTHERS MODULES *************************************************************************/#define ULPD_BASE_ADDR_ARM 0xFFFE0800 /* 0xFFFE0800 */#define MAILBOX_BASE_ADDR_ARM 0xFFFCF000 /* 0xFFFBF000 *//************************************************************************ MEMORIES *************************************************************************/#define SDRAM_BASE_ADDR_ARM 0x10000000#define SRAM_BASE_ADDR_ARM 0x20000000#define SECRAM_BASE_ADDR_ARM 0x00200000#define SECFUSE_BASE_ADDR_ARM 0x00210000#define CS0_BASE_ADDR_ARM 0x00000000#define CS1_BASE_ADDR_ARM 0x04000000#define CS2_BASE_ADDR_ARM 0x08000000#define CS3_BASE_ADDR_ARM 0x0c000000#define MPUI_BASE_ADDRESS 0xE0000000/************************************************************************ EMIFS MODULE *************************************************************************/#define COMPACTFLASH_BASE_ADDR_ARM 0xFFFE2800/************************************************************************ STATIC SWITCHES *************************************************************************/#define SSW_BASE_ADDR_ARM 0xFFFBC800#endif⌨️ 快捷键说明
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