2rhea.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
//                                                                             
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only 
//   Unauthorized reproduction and/or distribution is strictly prohibited.  
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work.  
//   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
//
//   Filename       	: Rhea_Bridge.h
//
//
//===============================================================================

#ifndef _RHEA_BRIDGE_HH
#define _RHEA_BRIDGE_HH
 
#include "top.h"
#define RHEA_ADDR_MASK	0x0000FFFF 


// Bridge identifier
//-----------------------
#define BRIDGE_1 	0
#define BRIDGE_2 	1

//Register list
//-----------------------
#define RHEA_CNTL  	    0
#define RHEA_BUS_ALLOC      1
#define RHEA_ARM_RHEA       2
#define RHEA_ENHANCED_REG   3
#define RHEA_DEBUG_ADDRESS  4
#define RHEA_DATA_LSB       5
#define RHEA_DATA_MSB       6
#define RHEA_DEBUG_CTRL     7

//  MEM_RHEA_BRIDGE_SUPERVISOR_ADR is the adress for the internal Rhea Bridge
//  MEM_RHEA_BRIDGE2_SUPERVISOR_ADR is the adress for the external Rhea Bridge
//----------------------------------------------------------------------------

// Base Address of Rhea Bridge configuration register only accessible in Supervisor Mode Read/Write
#define RHEA_BRIDGE_SUPERVISOR_ADDR  MEM_RHEA_BRIDGE_SUPERVISOR_ADDR
#define RHEA_BRIDGE2_SUPERVISOR_ADDR  MEM_RHEA_BRIDGE2_SUPERVISOR_ADDR

// Base Address of Rhea Bridge configuration register User Mode Read Only 
#define RHEA_BRIDGE_USER_ADDR        MEM_RHEA_BRIDGE_USER_ADDR
#define RHEA_BRIDGE2_USER_ADDR       MEM_RHEA_BRIDGE2_USER_ADDR


//--------------------------------------------------------------------------------
//          RHEA CONTROL 16 BITS REGISTER FOR BOTH INTERNAL AND EXTERNAL RHEAS     
//--------------------------------------------------------------------------------

#define RHEA_CNTL_REG_OFFSET 						0x00

#define RHEA_CNTL_REG_SUPERVISOR_ADDR 	( RHEA_BRIDGE_SUPERVISOR_ADDR + RHEA_CNTL_REG_OFFSET )
#define RHEA_CNTL_REG_USER_ADDR       	( RHEA_BRIDGE_USER_ADDR + RHEA_CNTL_REG_OFFSET )

#define RHEA2_CNTL_REG_SUPERVISOR_ADDR 	( RHEA_BRIDGE2_SUPERVISOR_ADDR + RHEA_CNTL_REG_OFFSET )
#define RHEA2_CNTL_REG_USER_ADDR       	( RHEA_BRIDGE2_USER_ADDR + RHEA_CNTL_REG_OFFSET )

//RHEA_CNTL
//-----------
#define RHEA_ACCESSFACTOR_VAL_0      0
#define RHEA_ACCESSFACTOR_VAL_1      1
#define RHEA_ACCESSFACTOR_VAL_2      2
#define RHEA_ACCESSFACTOR_VAL_3      3
#define RHEA_ACCESSFACTOR_VAL_4      4
#define RHEA_ACCESSFACTOR_VAL_5      5
#define RHEA_ACCESSFACTOR_VAL_6      6
#define RHEA_ACCESSFACTOR_VAL_7      7
#define RHEA_ACCESSFACTOR_VAL_8      8
#define RHEA_ACCESSFACTOR_VAL_9      9
#define RHEA_ACCESSFACTOR_VAL_10     10
#define RHEA_ACCESSFACTOR_VAL_11     11
#define RHEA_ACCESSFACTOR_VAL_12     12
#define RHEA_ACCESSFACTOR_VAL_13     13
#define RHEA_ACCESSFACTOR_VAL_14     14
#define RHEA_ACCESSFACTOR_VAL_15     15

#define     RHEA_ACCESS_FACTOR0_POS             0
#define     RHEA_ACCESS_FACTOR0_NUMB            4
#define     RHEA_ACCESS_FACTOR0_RESET_VAL       1
//------------------------------------

#define     RHEA_ACCESS_FACTOR1_POS             4
#define     RHEA_ACCESS_FACTOR1_NUMB            4
#define     RHEA_ACCESS_FACTOR1_RESET_VAL       1

//------------------------------------
#define     RHEA_ACCESS_TIMEOUT_POS             8
#define     RHEA_ACCESS_TIMEOUT_NUMB            8
#define     RHEA_ACCESS_TIMEOUT_RESET_VAL       0xFF

 
//--------------------------------------------------------------------------------
//          RHEA BUS ALLOC 4 BITS REGISTER  FOR BOTH INTERNAL AND EXTERNAL RHEAS               
//--------------------------------------------------------------------------------
#define RHEA_BUS_ALLOC_REG_OFFSET 					0x04

#define RHEA_BUS_ALLOC_REG_SUPERVISOR_ADDR  ( RHEA_BRIDGE_SUPERVISOR_ADDR + RHEA_BUS_ALLOC_REG_OFFSET )
#define RHEA_BUS_ALLOC_REG_USER_ADDR  			( RHEA_BRIDGE_USER_ADDR + RHEA_BUS_ALLOC_REG_OFFSET )

#define RHEA2_BUS_ALLOC_REG_SUPERVISOR_ADDR ( RHEA_BRIDGE2_SUPERVISOR_ADDR + RHEA_BUS_ALLOC_REG_OFFSET )
#define RHEA2_BUS_ALLOC_REG_USER_ADDR  			( RHEA_BRIDGE2_USER_ADDR + RHEA_BUS_ALLOC_REG_OFFSET )
 
//RHEA_BUS_ALLOC
//---------------
typedef enum { RHEA_PRIORITY_TO_ARM          = 0,
               RHEA_PRIORITY_TO_DMA_ACCESS_1 = 1,
               RHEA_PRIORITY_TO_DMA_ACCESS_2 = 2,
               RHEA_PRIORITY_TO_DMA_ACCESS_3 = 3,
               RHEA_PRIORITY_TO_DMA_ACCESS_4 = 4,
               RHEA_PRIORITY_TO_DMA_ACCESS_5 = 5,
               RHEA_PRIORITY_TO_DMA_ACCESS_6 = 6,
               RHEA_PRIORITY_TO_DMA_ACCESS_7 = 7
} RheaPriority_t;


#define     RHEA_PRIORITY_POS                   0                       
#define     RHEA_PRIORITY_NUMB                  2
#define     RHEA_PRIORITY_RESET_VAL             1
//------------------------------------
                       
#define     RHEA_ENABLE_PRIORITY                0                       
#define     RHEA_DISABLE_PRIORITY               1                       

#define     RHEA_PRIORITY_EN_POS                3
#define     RHEA_PRIORITY_EN_NUMB               1
#define     RHEA_PRIORITY_EN_RESET_VAL          1




//------------------------------------------------------------------------------------------
//          ARM RHEA CONTROL 4 BITS REGISTER FOR BOTH INTERNAL AND EXTERNAL RHEAS 
//------------------------------------------------------------------------------------------
#define RHEA_ARM_CONTROL_REG_OFFSET 						0x08

#define RHEA_ARM_CONTROL_REG_SUPERVISOR_ADDR   	( RHEA_BRIDGE_SUPERVISOR_ADDR + RHEA_ARM_CONTROL_REG_OFFSET )
#define RHEA_ARM_CONTROL_REG_USER_ADDR   				( RHEA_BRIDGE_USER_ADDR + RHEA_ARM_CONTROL_REG_OFFSET )

#define RHEA2_ARM_CONTROL_REG_SUPERVISOR_ADDR   ( RHEA_BRIDGE2_SUPERVISOR_ADDR + RHEA_ARM_CONTROL_REG_OFFSET )
#define RHEA2_ARM_CONTROL_REG_USER_ADDR   			( RHEA_BRIDGE2_USER_ADDR + RHEA_ARM_CONTROL_REG_OFFSET )

//RHEA_ARM_RHEA_CNTL
//---------------
#define     RHEA_WRITE_BUFFER_ENABLE            1                       
#define     RHEA_WRITE_BUFFER_DISABLE           0                       

#define     RHEA_WBUFF_EN0_POS                  0                       
#define     RHEA_WBUFF_EN0_NUMB                 1                     
#define     RHEA_WBUFF_EN0_RESET_VAL            0                     
//------------------------------------

#define     RHEA_WBUFF_EN1_POS                  1                       
#define     RHEA_WBUFF_EN1_NUMB                 1                     
#define     RHEA_WBUFF_EN1_RESET_VAL            0                     


 
//----------------------------------------------------------------------------------------------------
//          ENHANCED RHEA CONTROL 4 BITS REGISTER  FOR BOTH INTERNAL AND EXTERNAL RHEAS 
//----------------------------------------------------------------------------------------------------

#define RHEA_ENHANCED_CONTROL_REG_OFFSET 0x0C

#define RHEA_ENHANCED_CONTROL_REG_SUPERVISOR_ADDR   ( RHEA_BRIDGE_SUPERVISOR_ADDR + RHEA_ENHANCED_CONTROL_REG_OFFSET )
#define RHEA_ENHANCED_CONTROL_REG_USER_ADDR   			( RHEA_BRIDGE_USER_ADDR + RHEA_ENHANCED_CONTROL_REG_OFFSET )

#define RHEA2_ENHANCED_CONTROL_REG_SUPERVISOR_ADDR  ( RHEA_BRIDGE2_SUPERVISOR_ADDR + RHEA_ENHANCED_CONTROL_REG_OFFSET )
#define RHEA2_ENHANCED_CONTROL_REG_USER_ADDR   			( RHEA_BRIDGE2_USER_ADDR + RHEA_ENHANCED_CONTROL_REG_OFFSET )

//ENHANCED_RHEA_CNTL
//---------------
#define     RHEA_TIMEOUT_ENABLE                 1                       
#define     RHEA_TIMEOUT_DISABLE                0                       

#define     RHEA_TIMEOUT_EN_POS                 0                       
#define     RHEA_TIMEOUT_EN_NUMB                1                       
#define     RHEA_TIMEOUT_EN_RESET_VAL           1
//------------------------------------
                       
#define     RHEA_MASK_IT                        1                       
#define     RHEA_UNMASK_IT                      0

#define     RHEA_MASK_IT_POS                    1                       
#define     RHEA_MASK_IT_NUMB                   1                       
#define     RHEA_MASK_IT_RESET_VAL              1                      
//------------------------------------
                       
#define     RHEA_HIGH_FREQ                      1                       
#define     RHEA_LOW_FREQ                       0                      

#define     RHEA_HIGH_FREQ_POS                  2                       
#define     RHEA_HIGH_FREQ_NUMB                 1                       
#define     RHEA_HIGH_FREQ_RESET_VAL            1                       
//------------------------------------

 
#define     RHEA_ABORT_ENABLE                   0                       
#define     RHEA_ABORT_DISABLE                  1                      

#define     RHEA_ABORT_POS                      3                       
#define     RHEA_ABORT_NUMB                     1 
#define     RHEA_ABORT_RESET_VAL                1                       

//---------------------------------------------------------------------------------------------------
//          DEBUG ADDRESS REGISTER  FOR BOTH INTERNAL AND EXTERNAL RHEAS 
//---------------------------------------------------------------------------------------------------

#define RHEA_ADDRESS_DEBUG_REG_OFFSET 			0x10
#define RHEA_ADDRESS_DEBUG_REG_ADDR  				( RHEA_BRIDGE_USER_ADDR + RHEA_ADDRESS_DEBUG_REG_OFFSET )
#define RHEA2_ADDRESS_DEBUG_REG_ADDR  			( RHEA_BRIDGE2_USER_ADDR + RHEA_ADDRESS_DEBUG_REG_OFFSET )
//DEBUG_ADDRESS
//---------------

#define     RHEA_DEBUG_ADDRESS_POS                 0                       
#define     RHEA_DEBUG_ADDRESS_NUMB                16                       
#define     RHEA_DEBUG_ADDRESS_RESET_VAL           0xFFFF                       
//------------------------------------

 
//----------------------------------------------------------------------------------------------------
//          DEBUG DATA LSB REGISTER FOR BOTH INTERNAL AND EXTERNAL RHEAS 
//----------------------------------------------------------------------------------------------------

#define RHEA_DEBUG_DATA_LSB_REG_OFFSET 	0x14
#define RHEA_DEBUG_DATA_LSB_REG_ADDR  	( RHEA_BRIDGE_USER_ADDR + RHEA_DEBUG_DATA_LSB_REG_OFFSET )
#define RHEA2_DEBUG_DATA_LSB_REG_ADDR  	( RHEA_BRIDGE2_USER_ADDR + RHEA_DEBUG_DATA_LSB_REG_OFFSET )
//DATA_DBG_LOW
//---------------

#define     RHEA_DATA_DBG_LOW_POS                 0                       
#define     RHEA_DATA_DBG_LOW_NUMB                16                       
#define     RHEA_DATA_DBG_LOW_RESET_VAL           0xFFFF                       
//------------------------------------
                        


//----------------------------------------------------------------------------------------------------
//         DEBUG DATA MSB  16 BITS REGISTER FOR BOTH INTERNAL AND EXTERNAL RHEAS 
//----------------------------------------------------------------------------------------------------
#define RHEA_DEBUG_DATA_MSB_REG_OFFSET 	0x18
#define RHEA_DEBUG_DATA_MSB_REG_ADDR  	( RHEA_BRIDGE_USER_ADDR + RHEA_DEBUG_DATA_MSB_REG_OFFSET )
#define RHEA2_DEBUG_DATA_MSB_REG_ADDR  	( RHEA_BRIDGE2_USER_ADDR + RHEA_DEBUG_DATA_MSB_REG_OFFSET )

//DATA_DBG_HIGH