error.h~

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

#define            RHSW_ARM_RHSW_ARM_CNF_CIPHER_BAD_RESET_VALUE                                    0x290C
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_BAD_RESET_VALUE                                    0x290D

#define            RHSW_ARM_RHSW_ARM_CNF_MCSI1_BAD_ACCESS                                          0x292F
#define            RHSW_ARM_RHSW_ARM_STA_MCSI1_BAD_ACCESS                                          0x2930
#define            RHSW_ARM_RHSW_ARM_CNF_MCSI2_BAD_ACCESS                                          0x2931
#define            RHSW_ARM_RHSW_ARM_STA_MCSI2_BAD_ACCESS                                          0x2932
#define            RHSW_ARM_RHSW_ARM_CNF_TPU_BAD_ACCESS                                            0x2933
#define            RHSW_ARM_RHSW_ARM_STA_TPU_BAD_ACCESS                                            0x2934
#define            RHSW_ARM_RHSW_ARM_CNF_TSP_BAD_ACCESS                                            0x2935
#define            RHSW_ARM_RHSW_ARM_STA_TSP_BAD_ACCESS                                            0x2936
#define            RHSW_ARM_RHSW_ARM_CNF_GEA3_BAD_ACCESS                                           0x2937
#define            RHSW_ARM_RHSW_ARM_STA_GEA3_BAD_ACCESS                                           0x2938
#define            RHSW_ARM_RHSW_ARM_CNF_USIM_BAD_ACCESS                                           0x2939
#define            RHSW_ARM_RHSW_ARM_STA_USIM_BAD_ACCESS                                           0x293A
#define            RHSW_ARM_RHSW_ARM_CNF_CIPHER_BAD_ACCESS                                         0x293B
#define            RHSW_ARM_RHSW_ARM_STA_CIPHER_BAD_ACCESS                                         0x293C

#define            ELCD_CONTROL_REG_BAD_RESET_VALUE                                                0x2A00
#define            ELCD_ONOFFTIME_REG_BAD_RESET_VALUE                                              0x2A01
#define            ELCD_DMAIT_REG_BAD_RESET_VALUE                                                  0x2A02
#define            ELCD_TE_REG_BAD_RESET_VALUE                                                     0x2A03
#define            ELCD_ELCDCTL_REG_BAD_RESET_VALUE                                                0x2A04
#define            ELCD_CMDTX_REG_BAD_RESET_VALUE                                                  0x2A05
#define            ELCD_DATATX_REG_BAD_RESET_VALUE                                                 0x2A06
#define            ELCD_COUNTERRX_REG_BAD_RESET_VALUE                                              0x2A07
#define            ELCD_DATARX_REG_BAD_RESET_VALUE                                                 0x2A08
#define            ELCD_STATUS_REG_BAD_RESET_VALUE                                                  0x2A09
#define            ELCD_PIXELPOS_REG_BAD_RESET_VALUE                                               0x2A0A
#define            ELCD_CYCLE1_REG1_BAD_RESET_VALUE                                                0x2A0B
#define            ELCD_CYCLE1_REG2_BAD_RESET_VALUE                                                0x2A0C
#define            ELCD_CYCLE1_REG3_BAD_RESET_VALUE                                                0x2A0D
#define            ELCD_CYCLE1_REG4_BAD_RESET_VALUE                                                0x2A0E
#define            ELCD_CYCLE1_REG5_BAD_RESET_VALUE                                                0x2A0F
#define            ELCD_CYCLE2_REG1_BAD_RESET_VALUE                                                0x2A10
#define            ELCD_CYCLE2_REG2_BAD_RESET_VALUE                                                0x2A11
#define            ELCD_CYCLE2_REG3_BAD_RESET_VALUE                                                0x2A12
#define            ELCD_CYCLE3_REG1_BAD_RESET_VALUE                                                0x2A13
#define            ELCD_CYCLE3_REG2_BAD_RESET_VALUE                                                0x2A14
#define            ELCD_REVNB_REG_BAD_RESET_VALUE                                                  0x2A15
#define            ELCD_COUNTERTX_REG_BAD_RESET_VALUE                                              0x2A16

#define            ELCD_CONTROL_REG_BAD_ACCESS                                                     0x2A16
#define            ELCD_ONOFFTIME_REG_BAD_ACCESS                                                   0x2A17
#define            ELCD_DMAIT_REG_BAD_ACCESS                                                       0x2A18
#define            ELCD_TE_REG_BAD_ACCESS                                                          0x2A19
#define            ELCD_ELCDCTL_REG_BAD_ACCESS                                                     0x2A1A
#define            ELCD_CMDTX_REG_BAD_ACCESS                                                       0x2A1B
#define            ELCD_DATATX_REG_BAD_ACCESS                                                      0x2A1C
#define            ELCD_COUNTERRX_REG_BAD_ACCESS                                                   0x2A1D
#define            ELCD_DATARX_REG_BAD_ACCESS                                                      0x2A1E
#define            ELCD_STATUS_REG_BAD_ACCESS                                                      0x2A1F
#define            ELCD_PIXELPOS_REG_BAD_ACCESS                                                    0x2A20
#define            ELCD_CYCLE1_REG1_BAD_ACCESS                                                     0x2A21
#define            ELCD_CYCLE1_REG2_BAD_ACCESS                                                     0x2A22
#define            ELCD_CYCLE1_REG3_BAD_ACCESS                                                     0x2A23
#define            ELCD_CYCLE1_REG4_BAD_ACCESS                                                     0x2A24
#define            ELCD_CYCLE1_REG5_BAD_ACCESS                                                     0x2A25
#define            ELCD_CYCLE2_REG1_BAD_ACCESS                                                     0x2A26
#define            ELCD_CYCLE2_REG2_BAD_ACCESS                                                     0x2A27
#define            ELCD_CYCLE2_REG3_BAD_ACCESS                                                     0x2A28
#define            ELCD_CYCLE3_REG1_BAD_ACCESS                                                     0x2A29
#define            ELCD_CYCLE3_REG2_BAD_ACCESS                                                     0x2A2A
#define            ELCD_REVNB_REG_BAD_ACCESS                                                       0x2A2B
#define            ELCD_COUNTERTX_REG_BAD_ACCESS                                                   0x2A2C

#define            ELCD_TIMEOUT                                                                    0x2A2C
#define            ELCD_COMPARAISON_FAILURE                                                        0x2A2D
#define            ELCD_COMMAND_ERROR                                                              0x2A2E
#define            ELCD_DMA_ERROR                                                                  0x2A2F
#define            ELCD_DMA_TIMEOUT                                                                0x2A30
#define            ELCD_FSM_TIMEOUT                                                                0x2A31
#define            ELCD_DMA_UNKNOWN_ERROR                                                          0x2A32
#define            ELCD_FIRST_PIXEL_COMPARAISON_FAILURE                                            0x2A33

#define            LCD_DMA_0_INT_ERROR                                                     	   0x2B00
#define            LCD_DMA_LCD_INT_ERROR                                                     	   0x2B01
#define            LCD_INT_ERROR                                                      		   0x2B02

#define            ULPD_COUNTER_32_LSB_REG_BAD_RESET_VALUE                                         0x2C00
#define            ULPD_COUNTER_32_MSB_REG_BAD_RESET_VALUE                                         0x2C01
#define            ULPD_COUNTER_HIGH_FREQ_LSB_REG_BAD_RESET_VALUE                                  0x2C02
#define            ULPD_COUNTER_HIGH_FREQ_MSB_REG_BAD_RESET_VALUE                                  0x2C03
#define            ULPD_GAUGING_CTRL_REG_BAD_RESET_VALUE                                           0x2C04
#define            ULPD_IT_STATUS_REG_BAD_RESET_VALUE                                              0x2C05
#define            ULPD_SETUP_26M_REG_BAD_RESET_VALUE                                              0x2C06
#define            ULPD_SETUP_SLICER_REG_BAD_RESET_VALUE                                           0x2C07
#define            ULPD_SETUP_VTCXO_REG_BAD_RESET_VALUE                                            0x2C08
#define            ULPD_CLOCK_CTRL_REG_BAD_RESET_VALUE                                             0x2C09
#define            ULPD_SOFT_REQ_REG_BAD_RESET_VALUE                                               0x2C0A
#define            ULPD_STATUS_REQ_REG_BAD_RESET_VALUE                                             0x2C0B
#define            ULPD_APLL_CTRL_STATUS_BAD_RESET_VALUE                                           0x2C0C
#define            ULPD_POWER_CTRL_REG_BAD_RESET_VALUE                                             0x2C0D
#define            ULPD_SLEEP_STATUS_BAD_RESET_VALUE                                               0x2C0E
#define            ULPD_SETUP_RF_REG_BAD_RESET_VALUE                                               0x2C0F
#define            ULPD_SOFT_DISABLE_REQ_REG_BAD_RESET_VALUE                                       0x2C10
#define            ULPD_RESET_STATUS_BAD_RESET_VALUE                                               0x2C11
#define            ULPD_REVISION_NUMBER_BAD_RESET_VALUE                                            0x2C12
#define            ULPD_CLK_IO_CTRL_REG_BAD_RESET_VALUE                                            0x2C13
#define            ULPD_ENA_MEMORY_RETENTION_REG_BAD_RESET_VALUE                                   0x2C14
#define            ULPD_INC_FRAC_REG_BAD_RESET_VALUE                                               0x2C15
#define            ULPD_INC_SIXTEENTH_REG_BAD_RESET_VALUE                                          0x2C16
#define            ULPD_SETUP_FRAME_REG_BAD_RESET_VALUE                                            0x2C17
#define            ULPD_GSM_TIMER_INIT_REG_BAD_RESET_VALUE                                         0x2C18
#define            ULPD_GSM_TIMER_IT_REG_BAD_RESET_VALUE                                           0x2C19
#define            ULPD_GSM_TIMER_VALUE_REG_BAD_RESET_VALUE                                        0x2C1A
#define            ULPD_GSM_TIMER_CTRL_REG_BAD_RESET_VALUE                                         0x2C1B
#define            ULPD_CLOCK_GSM_REG_BAD_RESET_VALUE                                              0x2C1C
#define            ULPD_CLOCK_26M_CTRL_BAD_RESET_VALUE                                             0x2C1D
#define            ULPD_ARM_GSM_COUNTER_LSB_REG_BAD_RESET_VALUE                                    0x2C1E
#define            ULPD_ARM_GSM_COUNTER_MSB_REG_BAD_RESET_VALUE                                    0x2C1F
#define            ULPD_DSP_GSM_COUNTER_LSB_REG_BAD_RESET_VALUE                                    0x2C20
#define            ULPD_DSP_GSM_COUNTER_MSB_REG_BAD_RESET_VALUE                                    0x2C21
#define            ULPD_SIXTEENTH_START_REG_BAD_RESET_VALUE                                        0x2C22
#define            ULPD_SIXTEENTH_STOP_REG_BAD_RESET_VALUE                                         0x2C23


#define            ULPD_COUNTER_32_LSB_REG_BAD_ACCESS                                              0x2D01
#define            ULPD_COUNTER_32_MSB_REG_BAD_ACCESS                                              0x2D02
#define            ULPD_COUNTER_HIGH_FREQ_LSB_REG_BAD_ACCESS                                       0x2D03
#define            ULPD_COUNTER_HIGH_FREQ_MSB_REG_BAD_ACCESS                                       0x2D04
#define            ULPD_GAUGING_CTRL_REG_BAD_ACCESS                                                0x2D05
#define            ULPD_IT_STATUS_REG_BAD_ACCESS                                                   0x2D06
#define            ULPD_SETUP_26M_REG_BAD_ACCESS                                                   0x2D07
#define            ULPD_SETUP_SLICER_REG_BAD_ACCESS                                                0x2D08
#define            ULPD_SETUP_VTCXO_REG_BAD_ACCESS                                                 0x2D09
#define            ULPD_CLOCK_CTRL_REG_BAD_ACCESS                                                  0x2D0A
#define            ULPD_SOFT_REQ_REG_BAD_ACCESS                                                    0x2D0B
#define            ULPD_STATUS_REQ_REG_BAD_ACCESS                                                  0x2D0C 
#define            ULPD_PLL_DIV_REG_BAD_ACCESS                                                     0x2D0D
#define            ULPD_APLL_CTRL_STATUS_BAD_ACCESS                                                0x2D0E
#define            ULPD_POWER_CTRL_REG_BAD_ACCESS                                                  0x2D0F
#define            ULPD_SLEEP_STATUS_BAD_ACCESS                                                    0x2D10
#define            ULPD_SETUP_RF_REG_BAD_ACCESS                                                    0x2D11
#define            ULPD_SOFT_DISABLE_REQ_REG_BAD_ACCESS                                            0x2D12
#define            ULPD_RESET_STATUS_BAD_ACCESS                                                    0x2D13
#define            ULPD_REVISION_NUMBER_BAD_ACCESS                                                 0x2D14
#define            ULPD_CLK_IO_CTRL_REG_BAD_ACCESS                                                 0x2D15
#define            ULPD_ENA_MEMORY_RETENTION_REG_BAD_ACCESS                                        0x2D16
#define            ULPD_INC_FRAC_REG_BAD_ACCESS                                                    0x2D17
#define            ULPD_INC_SIXTEENTH_REG_BAD_ACCESS                                               0x2D18
#define            ULPD_SETUP_FRAME_REG_BAD_ACCESS                                                 0x2D19
#define            ULPD_GSM_TIMER_INIT_REG_BAD_ACCESS                                              0x2D1A
#define            ULPD_GSM_TIMER_IT_REG_BAD_ACCESS                                                0x2D1B
#define            ULPD_GSM_TIMER_VALUE_REG_BAD_ACCESS                                             0x2D1C
#define            ULPD_GSM_TIMER_CTRL_REG_BAD_ACCESS                                              0x2D1D
#define            ULPD_CLOCK_GSM_REG_BAD_ACCESS                                                   0x2D1E
#define            ULPD_CLOCK_26M_CTRL_BAD_ACCESS                                                  0x2D1F

#define            CAMERA_CORE_SETUP_ERROR                                                         0x2E00
#define            CAMERA_CORE_DATA_CMP_FAILURE                                                    0x2E01

#endif