📄 wcdma_srca.h
字号:
//SRCH_DEBUG_PN_IQ
//-------------------------
#define SRCH_DEBUG_PN_IQ REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DEBUG_PN_IQ_OFFSET) << 2))
#define SRCH_DEBUG_PN_IQ_RES_VAL 0x00000000
//R/W
//No write to this reg are allowed
//-------------------------
//SRCH_DEBUG_IQ
//-------------------------
#define SRCH_DEBUG_IQ REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DEBUG_IQ_OFFSET) << 2))
#define SRCH_DEBUG_IQ_RES_VAL 0x00000000
//R/W
//No write to this reg are allowed
//-------------------------
//SRCH_DEBUG_TIME_STAMP
//-------------------------
#define SRCH_DEBUG_TIME_STAMP REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DEBUG_TIME_STAMP_OFFSET) << 2))
#define SRCH_DEBUG_TIME_STAMP_RES_VAL 0x00000000
//R/W
//No write to this reg are allowed
//-------------------------
//SRCH_DEBUG_SEARCHER_ON
//-------------------------
#define SRCH_DEBUG_SEARCHER_ON REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DEBUG_SEARCHER_ON_OFFSET) << 2))
#define SRCH_DEBUG_SEARCHER_ON_RES_VAL 0x00000000
//R/W
//No write to this reg are allowed
//-------------------------
//SRCH_DEBUG_VERSION_ID
//-------------------------
#define SRCH_DEBUG_VERSION_ID REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DEBUG_VERSION_ID_OFFSET) << 2))
#define SRCH_DEBUG_VERSION_ID_RES_VAL 0x
//R/W
//No write to this reg are allowed
//-------------------------
#define SRCH_RESET_RD_MASK 0x00000002
#define SRCH_RESET_WR_MASK 0x00000002
#define SRCH_CONTROL_RD_MASK 0x002FFF37
#define SRCH_CONTROL_WR_MASK 0x002FFF37
#define SRCH_CORRECTION_RD_MASK 0xFFFFFFFF
#define SRCH_CORRECTION_WR_MASK 0xFFFFFFFF
#define SRCH_COMMON_PARAMS_RD_MASK 0xFFFFFFFF
#define SRCH_COMMON_PARAMS_WR_MASK 0xFFFFFFFF
#define VARIABLE_DWELL_PARAMS_RD_MASK 0x00FF00FF
#define VARIABLE_DWELL_PARAMS_WR_MASK 0x00FF00FF
#define BATCH_DONE_STATUS_CLEAR_RD_MASK 0x00000002
#define BATCH_DONE_STATUS_CLEAR_WR_MASK 0x00000002
#define SRCH_START_TIME_RD_MASK 0x0003FFFF
#define SRCH_START_TIME_WR_MASK 0x0003FFFF
#define SRCH_DWELL_AND_RES_0_RD_MASK 0x07F707F7
#define SRCH_DWELL_AND_RES_0_WR_MASK 0x07F707F7
#define SRCH_WIN_0_RD_MASK 0x3FFFFFFF
#define SRCH_WIN_0_WR_MASK 0x3FFFFFFF
#define SRCH_DWELL_AND_RES_1_RD_MASK 0x07F707F7
#define SRCH_DWELL_AND_RES_1_WR_MASK 0x07F707F7
#define SRCH_WIN_1_RD_MASK 0x3FFFFFFF
#define SRCH_WIN_1_WR_MASK 0x3FFFFFFF
#define SRCH_DWELL_AND_RES_2_RD_MASK 0x07F707F7
#define SRCH_DWELL_AND_RES_2_WR_MASK 0x07F707F7
#define SRCH_WIN_2_RD_MASK 0x3FFFFFFF
#define SRCH_WIN_2_WR_MASK 0x3FFFFFFF
#define SRCH_DWELL_AND_RES_3_RD_MASK 0x07F707F7
#define SRCH_DWELL_AND_RES_3_WR_MASK 0x07F707F7
#define SRCH_WIN_3_RD_MASK 0x3FFFFFFF
#define SRCH_WIN_3_WR_MASK 0x3FFFFFFF
#define SRCH_DWELL_AND_RES_4_RD_MASK 0x07F707F7
#define SRCH_DWELL_AND_RES_4_WR_MASK 0x07F707F7
#define SRCH_WIN_4_RD_MASK 0x3FFFFFFF
#define SRCH_WIN_4_WR_MASK 0x3FFFFFFF
#define SRCH_DWELL_AND_RES_5_RD_MASK 0x07F707F7
#define SRCH_DWELL_AND_RES_5_WR_MASK 0x07F707F7
#define SRCH_WIN_5_RD_MASK 0x3FFFFFFF
#define SRCH_WIN_5_WR_MASK 0x3FFFFFFF
#define SRCH_DWELL_AND_RES_6_RD_MASK 0x07F707F7
#define SRCH_DWELL_AND_RES_6_WR_MASK 0x07F707F7
#define SRCH_WIN_6_RD_MASK 0x3FFFFFFF
#define SRCH_WIN_6_WR_MASK 0x3FFFFFFF
#define SRCH_DWELL_AND_RES_7_RD_MASK 0x07F707F7
#define SRCH_DWELL_AND_RES_7_WR_MASK 0x07F707F7
#define SRCH_WIN_7_RD_MASK 0x3FFFFFFF
#define SRCH_WIN_7_WR_MASK 0x3FFFFFFF
#define BATCH_DONE_STATUS_RD_MASK 0x00000001
//The BATCH_DONE_STATUS reg has no write-able bits
#define SRCH_RESULT_READY_RD_MASK 0x000000FF
//The SRCH_RESULT_READY reg has no write-able bits
#define SRCH_NUM_COHERENT_DWELL_RD_MASK 0xFFFFFFFF
//The SRCH_NUM_COHERENT_DWELL reg has no write-able bits
#define SRCH_DEBUG_CAPTURE_VQDS_RD_MASK 0x00000001
#define SRCH_DEBUG_CAPTURE_VQDS_WR_MASK 0x00000001
#define SRCH_DEBUG_PN_IQ_RD_MASK 0xFFFFFFFF
//The SRCH_DEBUG_PN_IQ reg has no write-able bits
#define SRCH_DEBUG_IQ_RD_MASK 0xFFFFFFFF
//The SRCH_DEBUG_IQ reg has no write-able bits
#define SRCH_DEBUG_TIME_STAMP_RD_MASK 0x0000FFFF
//The SRCH_DEBUG_TIME_STAMP reg has no write-able bits
#define SRCH_DEBUG_SEARCHER_ON_RD_MASK 0x00000001
//The SRCH_DEBUG_SEARCHER_ON reg has no write-able bits
#define SRCH_DEBUG_VERSION_ID_RD_MASK 0x0000FFFF
//The SRCH_DEBUG_VERSION_ID reg has no write-able bits
#define SRCH_DEBUG_VERSION_ID_RES_VAL 0x
//RAM Locations
//SRCH_PSC_RESULT_0
#define SRCH_PSC_RESULT_0_OFFSET 0x100
#define SRCH_PSC_RESULT_0 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_0_OFFSET) << 2))
#define SRCH_PSC_RESULT_0_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_0_WR_MASK 0x00003FFF
//-------------------------
//SRCH_PSC_RESULT_1
#define SRCH_PSC_RESULT_1_OFFSET 0x101
#define SRCH_PSC_RESULT_1 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_1_OFFSET) << 2))
#define SRCH_PSC_RESULT_1_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_1_WR_MASK 0x00003FFF
//-------------------------
//SRCH_PSC_RESULT_2
#define SRCH_PSC_RESULT_2_OFFSET 0x102
#define SRCH_PSC_RESULT_2 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_2_OFFSET) << 2))
#define SRCH_PSC_RESULT_2_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_2_WR_MASK 0x00003FFF
//-------------------------
//SRCH_PSC_RESULT_3
#define SRCH_PSC_RESULT_3_OFFSET 0x103
#define SRCH_PSC_RESULT_3 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_3_OFFSET) << 2))
#define SRCH_PSC_RESULT_3_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_3_WR_MASK 0x00003FFF
//-------------------------
//SRCH_PSC_RESULT_4
#define SRCH_PSC_RESULT_4_OFFSET 0x104
#define SRCH_PSC_RESULT_4 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_4_OFFSET) << 2))
#define SRCH_PSC_RESULT_4_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_4_WR_MASK 0x00003FFF
//-------------------------
//SRCH_PSC_RESULT_5
#define SRCH_PSC_RESULT_5_OFFSET 0x105
#define SRCH_PSC_RESULT_5 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_5_OFFSET) << 2))
#define SRCH_PSC_RESULT_5_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_5_WR_MASK 0x00003FFF
//-------------------------
//SRCH_PSC_RESULT_6
#define SRCH_PSC_RESULT_6_OFFSET 0x106
#define SRCH_PSC_RESULT_6 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_6_OFFSET) << 2))
#define SRCH_PSC_RESULT_6_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_6_WR_MASK 0x00003FFF
//-------------------------
//SRCH_PSC_RESULT_7
#define SRCH_PSC_RESULT_7_OFFSET 0x107
#define SRCH_PSC_RESULT_7 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_7_OFFSET) << 2))
#define SRCH_PSC_RESULT_7_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_7_WR_MASK 0x00003FFF
//-------------------------
//SRCH_PSC_RESULT_8
#define SRCH_PSC_RESULT_8_OFFSET 0x108
#define SRCH_PSC_RESULT_8 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_8_OFFSET) << 2))
#define SRCH_PSC_RESULT_8_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_8_WR_MASK 0x00003FFF
//-------------------------
//SRCH_PSC_RESULT_9
#define SRCH_PSC_RESULT_9_OFFSET 0x109
#define SRCH_PSC_RESULT_9 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_9_OFFSET) << 2))
#define SRCH_PSC_RESULT_9_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_9_WR_MASK 0x00003FFF
//-------------------------
//SRCH_PSC_RESULT_255
#define SRCH_PSC_RESULT_255_OFFSET 0x1ff
#define SRCH_PSC_RESULT_255 REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_PSC_RESULT_255_OFFSET) << 2))
#define SRCH_PSC_RESULT_255_RD_MASK 0x00003FFF
#define SRCH_PSC_RESULT_255_WR_MASK 0x00003FFF
// Function prototype
void WCDMA_SrcaTestResetValue(void);
void WCDMA_SrcaTestRegistersAccess(void);
#endif
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -