wcdma_srca.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//        TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2001,  (C) Copyright 2001 Texas Instruments. All rights reserved
//
//========================================================================


#include "wcdma_mapping.h"
#ifndef _wcdma_srca__H
#define _wcdma_srca__H

//Standard Register offset list


#define            SRCH_RESET_OFFSET                     0x00
#define            SRCH_CONTROL_OFFSET                     0x01
#define            SRCH_CORRECTION_OFFSET                     0x02
#define            SRCH_COMMON_PARAMS_OFFSET                     0x03
#define            VARIABLE_DWELL_PARAMS_OFFSET                     0x04
#define            BATCH_DONE_STATUS_CLEAR_OFFSET                     0x05
#define            SRCH_START_TIME_OFFSET                     0x06
#define            SRCH_DWELL_AND_RES_0_OFFSET                     0x0D
#define            SRCH_WIN_0_OFFSET                     0x0E
#define            SRCH_DWELL_AND_RES_1_OFFSET                     0x0F
#define            SRCH_WIN_1_OFFSET                     0x10
#define            SRCH_DWELL_AND_RES_2_OFFSET                     0x11
#define            SRCH_WIN_2_OFFSET                     0x12
#define            SRCH_DWELL_AND_RES_3_OFFSET                     0x13
#define            SRCH_WIN_3_OFFSET                     0x14
#define            SRCH_DWELL_AND_RES_4_OFFSET                     0x15
#define            SRCH_WIN_4_OFFSET                     0x16
#define            SRCH_DWELL_AND_RES_5_OFFSET                     0x17
#define            SRCH_WIN_5_OFFSET                     0x18
#define            SRCH_DWELL_AND_RES_6_OFFSET                     0x19
#define            SRCH_WIN_6_OFFSET                     0x1A
#define            SRCH_DWELL_AND_RES_7_OFFSET                     0x1B
#define            SRCH_WIN_7_OFFSET                     0x1C
#define            BATCH_DONE_STATUS_OFFSET                     0x1D
#define            SRCH_RESULT_READY_OFFSET                     0x1E
#define            SRCH_NUM_COHERENT_DWELL_OFFSET                     0x1F
#define            SRCH_DEBUG_CAPTURE_VQDS_OFFSET                     0x20
#define            SRCH_DEBUG_PN_IQ_OFFSET                     0x21
#define            SRCH_DEBUG_IQ_OFFSET                     0x22
#define            SRCH_DEBUG_TIME_STAMP_OFFSET                     0x23
#define            SRCH_DEBUG_SEARCHER_ON_OFFSET                     0x24
#define            SRCH_DEBUG_VERSION_ID_OFFSET                     0x25
//SRCH_RESET
//-------------------------
#define            SRCH_RESET                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_RESET_OFFSET) << 2))
#define            SRCH_RESET_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_CONTROL
//-------------------------
#define            SRCH_CONTROL                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_CONTROL_OFFSET) << 2))
#define            SRCH_CONTROL_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_CORRECTION
//-------------------------
#define            SRCH_CORRECTION                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_CORRECTION_OFFSET) << 2))
#define            SRCH_CORRECTION_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_COMMON_PARAMS
//-------------------------
#define            SRCH_COMMON_PARAMS                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_COMMON_PARAMS_OFFSET) << 2))
#define            SRCH_COMMON_PARAMS_RES_VAL                0x00000000
//R/W
//-------------------------



//VARIABLE_DWELL_PARAMS
//-------------------------
#define            VARIABLE_DWELL_PARAMS                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+VARIABLE_DWELL_PARAMS_OFFSET) << 2))
#define            VARIABLE_DWELL_PARAMS_RES_VAL                0x00000000
//R/W
//-------------------------



//BATCH_DONE_STATUS_CLEAR
//-------------------------
#define            BATCH_DONE_STATUS_CLEAR                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+BATCH_DONE_STATUS_CLEAR_OFFSET) << 2))
#define            BATCH_DONE_STATUS_CLEAR_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_START_TIME
//-------------------------
#define            SRCH_START_TIME                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_START_TIME_OFFSET) << 2))
#define            SRCH_START_TIME_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_DWELL_AND_RES_0
//-------------------------
#define            SRCH_DWELL_AND_RES_0                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DWELL_AND_RES_0_OFFSET) << 2))
#define            SRCH_DWELL_AND_RES_0_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_WIN_0
//-------------------------
#define            SRCH_WIN_0                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_WIN_0_OFFSET) << 2))
#define            SRCH_WIN_0_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_DWELL_AND_RES_1
//-------------------------
#define            SRCH_DWELL_AND_RES_1                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DWELL_AND_RES_1_OFFSET) << 2))
#define            SRCH_DWELL_AND_RES_1_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_WIN_1
//-------------------------
#define            SRCH_WIN_1                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_WIN_1_OFFSET) << 2))
#define            SRCH_WIN_1_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_DWELL_AND_RES_2
//-------------------------
#define            SRCH_DWELL_AND_RES_2                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DWELL_AND_RES_2_OFFSET) << 2))
#define            SRCH_DWELL_AND_RES_2_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_WIN_2
//-------------------------
#define            SRCH_WIN_2                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_WIN_2_OFFSET) << 2))
#define            SRCH_WIN_2_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_DWELL_AND_RES_3
//-------------------------
#define            SRCH_DWELL_AND_RES_3                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DWELL_AND_RES_3_OFFSET) << 2))
#define            SRCH_DWELL_AND_RES_3_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_WIN_3
//-------------------------
#define            SRCH_WIN_3                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_WIN_3_OFFSET) << 2))
#define            SRCH_WIN_3_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_DWELL_AND_RES_4
//-------------------------
#define            SRCH_DWELL_AND_RES_4                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DWELL_AND_RES_4_OFFSET) << 2))
#define            SRCH_DWELL_AND_RES_4_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_WIN_4
//-------------------------
#define            SRCH_WIN_4                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_WIN_4_OFFSET) << 2))
#define            SRCH_WIN_4_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_DWELL_AND_RES_5
//-------------------------
#define            SRCH_DWELL_AND_RES_5                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DWELL_AND_RES_5_OFFSET) << 2))
#define            SRCH_DWELL_AND_RES_5_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_WIN_5
//-------------------------
#define            SRCH_WIN_5                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_WIN_5_OFFSET) << 2))
#define            SRCH_WIN_5_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_DWELL_AND_RES_6
//-------------------------
#define            SRCH_DWELL_AND_RES_6                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DWELL_AND_RES_6_OFFSET) << 2))
#define            SRCH_DWELL_AND_RES_6_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_WIN_6
//-------------------------
#define            SRCH_WIN_6                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_WIN_6_OFFSET) << 2))
#define            SRCH_WIN_6_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_DWELL_AND_RES_7
//-------------------------
#define            SRCH_DWELL_AND_RES_7                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DWELL_AND_RES_7_OFFSET) << 2))
#define            SRCH_DWELL_AND_RES_7_RES_VAL                0x00000000
//R/W
//-------------------------



//SRCH_WIN_7
//-------------------------
#define            SRCH_WIN_7                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_WIN_7_OFFSET) << 2))
#define            SRCH_WIN_7_RES_VAL                0x00000000
//R/W
//-------------------------



//BATCH_DONE_STATUS
//-------------------------
#define            BATCH_DONE_STATUS                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+BATCH_DONE_STATUS_OFFSET) << 2))
#define            BATCH_DONE_STATUS_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//SRCH_RESULT_READY
//-------------------------
#define            SRCH_RESULT_READY                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_RESULT_READY_OFFSET) << 2))
#define            SRCH_RESULT_READY_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//SRCH_NUM_COHERENT_DWELL
//-------------------------
#define            SRCH_NUM_COHERENT_DWELL                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_NUM_COHERENT_DWELL_OFFSET) << 2))
#define            SRCH_NUM_COHERENT_DWELL_RES_VAL                0x00000000
//R/W
//No write to this reg are allowed
//-------------------------



//SRCH_DEBUG_CAPTURE_VQDS
//-------------------------
#define            SRCH_DEBUG_CAPTURE_VQDS                        REG32(WCDMA_CS_LB+((WCDMA_SRCA_BASE_ADDR+SRCH_DEBUG_CAPTURE_VQDS_OFFSET) << 2))
#define            SRCH_DEBUG_CAPTURE_VQDS_RES_VAL                0x00000000
//R/W
//-------------------------