dsp_clkm.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Filename             : dsp_clkm_a9.h

   Description          : Header file for the MPU DSP_CLM functions

   Project              : OMAP

   Author               : Achuta Thippana

   MACROS PROVIDED      :
  
 FUNCTIONS PROVIDED    :
===============================================================================
*/
#ifndef _DSP_CLKM__HH
#define _DSP_CLKM__HH

#include "global_types.h"
#include "mem.h"

#define DSP_CKCTL_REG_OFFSET      0x000
#define DSP_IDLECT1_REG_OFFSET    0x004
#define DSP_IDLECT2_REG_OFFSET    0x008
#define DSP_EWUPCT_REG_OFFSET     0x00C
#define DSP_RSTCT1_REG_OFFSET     0x010
#define DSP_RSTCT2_REG_OFFSET     0x014
#define DSP_SYSST_REG_OFFSET      0x018


#define DSP_CKCTL_REG_ADDR      (MEM_DSP_CLKM_ADDR + DSP_CKCTL_REG_OFFSET)
#define DSP_IDLECT1_REG_ADDR    (MEM_DSP_CLKM_ADDR + DSP_IDLECT1_REG_OFFSET)
#define DSP_IDLECT2_REG_ADDR    (MEM_DSP_CLKM_ADDR + DSP_IDLECT2_REG_OFFSET)
#define DSP_EWUPCT_REG_ADDR     (MEM_DSP_CLKM_ADDR + DSP_EWUPCT_REG_OFFSET)
#define DSP_SYSST_REG_ADDR      (MEM_DSP_CLKM_ADDR + DSP_SYSST_REG_OFFSET)
#define DSP_RSTCT1_REG_ADDR     (MEM_DSP_CLKM_ADDR + DSP_RSTCT1_REG_OFFSET)
#define DSP_RSTCT2_REG_ADDR     (MEM_DSP_CLKM_ADDR + DSP_RSTCT2_REG_OFFSET)


#define DSP_CKCTL_RESET_VAL      0x0190
#define DSP_IDLECT1_RESET_VAL    0x0040
#define DSP_IDLECT2_RESET_VAL    0x0000
#define DSP_EWUPCT_RESET_VAL     0x0000 
#define DSP_SYSST_RESET_VAL      0x0030 
#define DSP_RSTCT1_RESET_VAL     0x0000 
#define DSP_RSTCT2_RESET_VAL     0x0000 

#define DSP_CKCTL_MASK_VAL      0x01FF 
#define DSP_IDLECT1_MASK_VAL    0x01FF
#define DSP_IDLECT2_MASK_VAL    0x003F
#define DSP_EWUPCT_MASK_VAL     0x0000 /**??All bits reserved **/
#define DSP_SYSST_MASK_VAL      0x007F /**?? Bits [13:7] depend on the OMAP input pins, Masked out for now **/
#define DSP_RSTCT1_MASK_VAL     0x0000 /**??All bits reserved **/
#define DSP_RSTCT2_MASK_VAL     0x0001


#endif