📄 gdma_omap32.h
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//=====================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments -- For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited
// This product is protected under copyright law and trade secret law as
// an unpublished work.Created 2001,(C) Copyright 2001 Texas Instruments.
// All rights reserved.
//=====================================================================
#ifndef __GDMA_OMAP32_H__
#define __GDMA_OMAP32_H__
#include "gdma.h"
#ifndef MEM_RHEA_STROBE1_CS26_ADDR
#define MEM_RHEA_STROBE1_CS26_ADDR (MEM_RHEA_STROBE1_CS0_ADDR + 26 * MEM_RHEA_STROBE_LENGTH)
#define TMCR0_ADDR (MEM_RHEA_STROBE1_CS26_ADDR + 0x408)
#endif
#ifndef MEM_RHEA_STROBE1_CS27_ADDR
#define MEM_RHEA_STROBE1_CS27_ADDR (MEM_RHEA_STROBE1_CS0_ADDR + 27 * MEM_RHEA_STROBE_LENGTH)
#endif
#define LCD_CHANNEL_START_ADDRESS 0xFFFEE3C0
#define LCD_DMA_ACC(reg_select) REG16((LCD_CHANNEL_START_ADDRESS | (reg_select<<1)))
#define LCD_DMA_ACC32(reg_select) REG32((LCD_CHANNEL_START_ADDRESS | (reg_select<<2)))
// Total Number of channels
#define DMA_NUMBER_OF_CHANNEL_OMAP32 16
// ChannelNumb
#define DMA_CHANNEL_9 9
#define DMA_CHANNEL_10 10
#define DMA_CHANNEL_11 11
#define DMA_CHANNEL_12 12
#define DMA_CHANNEL_13 13
#define DMA_CHANNEL_14 14
#define DMA_CHANNEL_15 15
#define DMA_CHANNEL_LCD_OMAP32 31
// DMA Request inputs
#define DMA_SYNC_6 0x6
#define DMA_SYNC_7 0x7
#define DMA_SYNC_8 0x8
#define DMA_SYNC_9 0x9
#define DMA_SYNC_10 0xa
#define DMA_SYNC_11 0xb
#define DMA_SYNC_12 0xc
#define DMA_SYNC_13 0xd
#define DMA_SYNC_14 0xe
#define DMA_SYNC_15 0xf
#define DMA_SYNC_16 0x10
#define DMA_SYNC_17 0x11
#define DMA_SYNC_18 0x12
#define DMA_SYNC_19 0x13
#define DMA_SYNC_20 0x14
#define DMA_SYNC_21 0x15
#define DMA_SYNC_22 0x16
#define DMA_SYNC_23 0x17
#define DMA_SYNC_24 0x18
#define DMA_SYNC_25 0x19
#define DMA_SYNC_26 0x1a
#define DMA_SYNC_27 0x1b
#define DMA_SYNC_28 0x1c
#define DMA_SYNC_29 0x1d
#define DMA_SYNC_30 0x1e
#define DMA_SYNC_31 0x1f
//------------------------------------
// DMA global registers
//------------------------------------
#define DMA_GSCR 2
#define DMA_GRST 4
//------------------------------------
// DMA channel control registers
//------------------------------------
#define DMA_CSSA (DMA_CSSA_L >> 1)
#define DMA_CDSA (DMA_CDSA_L >> 1)
#define DMA_CSAC 12
#define DMA_CDAC 13
#define DMA_CDEI 14
#define DMA_CDFI 15
#define DMA_COLOR_L 16
#define DMA_COLOR_U 17
#define DMA_COLOR (DMA_COLOR_L >> 1)
#define DMA_CCR2 18
#define DMA_CLNK_CTRL 20
#define DMA_LCH_CTRL 21
//------------------------------------
// LCD channel registers
//------------------------------------
#define GDMA_LCD_CSDP 0
#define GDMA_LCD_CCR 1
#define GDMA_LCD_CTRL 2
#define GDMA_LCD_TOP_B1_L 4
#define GDMA_LCD_TOP_B1_U 5
#define GDMA_LCD_TOP_B1 (GDMA_LCD_TOP_B1_L >> 1)
#define GDMA_LCD_BOT_B1_L 6
#define GDMA_LCD_BOT_B1_U 7
#define GDMA_LCD_BOT_B1 (GDMA_LCD_BOT_B1_L >> 1)
#define GDMA_LCD_TOP_B2_L 8
#define GDMA_LCD_TOP_B2_U 9
#define GDMA_LCD_TOP_B2 (GDMA_LCD_TOP_B2_L >> 1)
#define GDMA_LCD_BOT_B2_L 10
#define GDMA_LCD_BOT_B2_U 11
#define GDMA_LCD_BOT_B2 (GDMA_LCD_BOT_B2_L >> 1)
#define GDMA_LCD_SRC_EI_B1 12
#define GDMA_LCD_SRC_FI_B1 13
#define GDMA_LCD_SRC_EI_B2 14
#define GDMA_LCD_SRC_FI_B2 15
#define GDMA_LCD_SRC_EN_B1 16
#define GDMA_LCD_SRC_EN_B2 17
#define GDMA_LCD_SRC_FN_B1 18
#define GDMA_LCD_SRC_FN_B2 19
#define GDMA_LCD_LCH_CTRL 21
#define GDMA_LCD_SRC_FI_HI_B1 26
#define GDMA_LCD_SRC_FI_HI_B2 27
//----------------------------------------
/* DMA_GSCR */
#define DMA_OMAP31_MAPPING_POS 3
#define DMA_OMAP31_MAPPING_NUMB 1
#define DMA_OMAP31_MAPPING_DISABLE 1
#define DMA_OMAP31_MAPPING_ENABLE 0
/* CSDP */
#define DMA_EMIFF 0x0
#define DMA_EMIFS 0x1
#define DMA_OCPT1 0x2
#define DMA_OCPT2 0x4
/* Defined in gdma.h
#define DMA_RHEA 0x3
#define DMA_RHEA_API 0x5
*/
/* DMA_CCR */
#undef DMA_SYNCNUMB_NUMB
#define DMA_SYNCNUMB_NUMB 5
//----------------------------------------
//OMAP_3.1CompatibleDisable
#define DMA_COMPATIBLE_DIS 0x1
#define DMA_COMPATIBLE_EN 0x0
#define DMA_COMPATIBLE_POS 10
#define DMA_COMPATIBLE_NUMB 1
#define DMA_COMPATIBLE_RESET_VAL 0
//----------------------------------------
//End Prog
#define DMA_ENDPROG_ON 0x1
#define DMA_ENDPROG_OFF 0x0
#define DMA_ENDPROG_POS 11
#define DMA_ENDPROG_NUMB 1
#define DMA_ENDPROG_RESET_VAL 0
//----------------------------------------
//DMA_CDEI
//----------------------
#define DMA_CDEI_POS 0
#define DMA_CDEI_NUMB 16
#define DMA_CDEI_MASK 0xFFFF
//----------------------------------------
//DMA_CDFI
//----------------------
#define DMA_CDFI_POS 0
#define DMA_CDFI_NUMB 16
#define DMA_CDFI_MASK 0xFFFF
//DMA_COLOR_L
//----------------------
#define DMA_COLOR_L_POS 0
#define DMA_COLOR_L_NUMB 16
#define DMA_COLOR_L_MASK 0xFFFF
//DMA_COLOR_U
//----------------------
#define DMA_COLOR_U_POS 0
#define DMA_COLOR_U_NUMB 16
#define DMA_COLOR_U_MASK 0xFFFF0000
//DMA_CCR2
//----------------------
#define DMA_CFE_ENABLE 1
#define DMA_CFE_DISABLE 0
#define DMA_CFE_POS 0
#define DMA_CFE_NUMB 1
#define DMA_TCE_ENABLE 1
#define DMA_TCE_DISABLE 0
#define DMA_TCE_POS 1
#define DMA_TCE_NUMB 1
#define DMA_BSE_ENABLE 1
#define DMA_BSE_DISABLE 0
#define DMA_BSE_POS 2
#define DMA_BSE_NUMB 1
#define DMA_PSE_ENABLE 1
#define DMA_PSE_DISABLE 0
#define DMA_PSE_POS 8
#define DMA_PSE_NUMB 1
//GDMA CLNK CTRL
#define DMA_LCH_TYP_2D 0x0
#define DMA_LCH_TYP_G 0x1
#define DMA_LCH_TYP_P 0x2
#define DMA_LCH_TYP_D 0x4
#define DMA_LCH_TYP_PD 0x7
#define DMA_LCH_INTERLEAVE_EN 0x1
#define DMA_LCH_INTERLEAVE_DIS 0x0
#define DMA_NXTCHID_POS 0
#define DMA_NXTCHID_NUMB 4
#define DMA_STOPLNK_POS 14
#define DMA_STOPLNK_NUMB 1
#define DMA_ENABLELNK_POS 15
#define DMA_ENABLELNK_NUMB 1
//GDMA LCH CTRL
#define DMA_LCHTYPE_POS 0
#define DMA_LCHTYPE_NUMB 4
#define DMA_LCHINTDIS_POS 15
#define DMA_LCHINTDIS_NUMB 1
/*******************************************************************************
//Define the Interrupt numbers for the DMA channels
*******************************************************************************/
#define INTH_FIQNIRQ_DMA_CH0_OMAP32 INTH_FIQNIRQ_DMA_CH0
#define INTH_FIQNIRQ_DMA_CH1_OMAP32 INTH_FIQNIRQ_DMA_CH1
#define INTH_FIQNIRQ_DMA_CH2_OMAP32 INTH_FIQNIRQ_DMA_CH2
#define INTH_FIQNIRQ_DMA_CH3_OMAP32 INTH_FIQNIRQ_DMA_CH3
#define INTH_FIQNIRQ_DMA_CH4_OMAP32 INTH_FIQNIRQ_DMA_CH4
#define INTH_FIQNIRQ_DMA_CH5_OMAP32 INTH_FIQNIRQ_DMA_CH5
#define INTH_FIQNIRQ_DMA_CH6_OMAP32 INTH_FIQNIRQ_25
#define INTH_FIQNIRQ_DMA_CH7_OMAP32 INTH_FIQNIRQ_12
#define INTH_FIQNIRQ_DMA_CH8_OMAP32 INTH_FIQNIRQ_14
#define INTH_FIQNIRQ_DMA_CH9_OMAP32 INTH_FIQNIRQ_15
#define INTH_FIQNIRQ_DMA_CH10_OMAP32 INTH_FIQNIRQ_17
#define INTH_FIQNIRQ_DMA_CH11_OMAP32 INTH_FIQNIRQ_18
#define INTH_FIQNIRQ_DMA_CH12_OMAP32 INTH_FIQNIRQ_26
#define INTH_FIQNIRQ_DMA_CH13_OMAP32 INTH_FIQNIRQ_28
#define INTH_FIQNIRQ_DMA_CH14_OMAP32 INTH_FIQNIRQ_29
#define INTH_FIQNIRQ_DMA_CH15_OMAP32 INTH_FIQNIRQ_31
#define INTH_FIQNIRQ_DMA_LCD_OMAP32 INTH_FIQNIRQ_25
// ----------------------------------------------------------
// Channel DMA descriptor structure
// ----------------------------------------------------------
typedef struct
{
BIT ChannelNumb:4;
//DMA_CSDP
//--------------------
BIT TypeSize:2;
BIT SrcPort:3;
BIT DestPort:3;
BIT SrcPack:1;
BIT DestPack:1;
BIT SrcBurst:2;
BIT DestBurst:2;
//DMA_CCR
//-----------------------
BIT SyncNumb:5;
BIT EventSync:1;//fs
BIT Priority:1;
BIT Enable:1;
BIT Autoinit:1;
BIT Repeat:1;
BIT OMAP31Disable:1;
BIT EndProg:1;
BIT SrcAddressMode:2;
BIT DestAddressMode:2;
//DMA_CICR
//----------------------
BIT TimeoutIntEnable:1;
BIT DropIntEnable:1;
BIT HalfFrameIntEnable:1;
BIT FrameIntEnable:1;
BIT LastFrameIntEnable:1;
BIT BlockIntEnable:1;
//DMA_CSCR
//----------------------
BIT TimeoutInt:1;
BIT DropInt:1;
BIT HalfFrameInt:1;
BIT FrameInt:1;
BIT LastFrameInt:1;
BIT BlockInt:1;
//DMA_CSSA L and U
//----------------------
UWORD32 SrcAdd;
//DMA_CDSA L and U
//----------------------
UWORD32 DestAdd;
//DMA_CEN
//----------------------
UWORD16 EltNumber;
//DMA_CFN
//----------------------
UWORD16 FrameNumber;
//DMA_CEI
//----------------------
UWORD16 EltIndex;
//DMA_CFI
//----------------------
UWORD16 FrameIndex;
//DMA_CDEI
//----------------------
UWORD16 DEltIndex;
//DMA_CDFI
//----------------------
UWORD16 DFrameIndex;
//DMA_COLOR
//----------------------
UWORD32 COLOR;
//DMA_CCR2
//----------------------
BIT CFE:1;
BIT TCE:1;
BIT BSE:1;
BIT PSE:1;
//DMA_LCH_CTRL
//----------------------
BIT LCH_TYPE:4;
BIT LCH_INTERLEAVE_DIS:1;
//DMA_CLNK_CTRL
//----------------------
BIT NXTLCH_ID:4;
BIT STOP_LNK:1;
BIT ENABLE_LNK:1;
//-------------------------------------------------------------------
//Patern use to prepare data to transfert (use for test only)
//------------------------------------------------------------
UWORD16 Pattern;
}
CHANNEL_DESCRIPTOR_OMAP32 ;
//=================================================================
//=================================================================
/* DMA_LCD_CSDP */
#define DMA_LCD_TYPE_SIZE_B1_POS 0
#define DMA_LCD_TYPE_SIZE_B1_NUMB 2
#define DMA_LCD_B1_PACK_POS 6
#define DMA_LCD_B1_PACK_NUMB 1
#define DMA_LCD_B1_BURST_POS 7
#define DMA_LCD_B1_BURST_NUMB 2
#define DMA_LCD_TYPE_SIZE_B2_POS 11
#define DMA_LCD_TYPE_SIZE_B2_NUMB 2
#define DMA_LCD_B2_PACK_POS 13
#define DMA_LCD_B2_PACK_NUMB 1
#define DMA_LCD_B2_BURST_POS 14
#define DMA_LCD_B2_BURST_NUMB 2
/* DMA_LCD_CCR */
#define DMA_LCD_BLOCKSYNC_POS 4
#define DMA_LCD_BLOCKSYNC_NUMB 1
#define DMA_LCD_PRIORITY_POS 6
#define DMA_LCD_PRIORITY_NUMB 1
#define DMA_LCD_ENABLE_POS 7
#define DMA_LCD_ENABLE_NUMB 1
#define DMA_LCD_AUTOINIT_POS 8
#define DMA_LCD_AUTOINIT_NUMB 1
#define DMA_LCD_REPEAT_POS 9
#define DMA_LCD_REPEAT_NUMB 1
#define DMA_LCD_COMPATIBLE_POS 10
#define DMA_LCD_COMPATIBLE_NUMB 1
#define DMA_LCD_ENDPROG_POS 11
#define DMA_LCD_ENDPROG_NUMB 1
#define DMA_LCD_B1_AMODE_POS 12
#define DMA_LCD_B1_AMODE_NUMB 2
#define DMA_LCD_B2_AMODE_POS 14
#define DMA_LCD_B2_AMODE_NUMB 2
/* DMA_LCD_CTRL */
#define DMA_LCD_EMIFF_SRC 0
#define DMA_LCD_OCPT1_SRC 1
#define DMA_LCD_OCPT2_SRC 2
#undef DMA_LCD_SRC_NUMB
#define DMA_LCD_SRC_NUMB 2
#define DMA_LCD_OMAP_DEST 0
#define DMA_LCD_EXT_DEST 1
#define DMA_LCD_DEST_POS 8
#define DMA_LCD_DEST_NUMB 1
#define DMA_LCD_DEST_RESET_VAL 0
#define DMA_LCD_TYPE_POS 0
#define DMA_LCD_TYPE_NUMB 4
//DMA_LCD_SRC_EI_B1
//---------------------------------------
#define DMA_LCD_SRC_EI_B1_POS 0
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