📄 mmu.h
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/*
-----------------------------------------------------------------------------
NAME : MMU_FineSmallPage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_FineSmallPage(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_FineTinyPage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_FineTinyPage(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_Section_Error -
DESCRIPTION : Build 1st level descriptor and address of this descriptor -
and set the 2 LSB of 1st level descriptor to "00" -
Write this descriptor into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_Section_Error (MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_CoarseLargePageError1 -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
and set the 2 LSB of 1st level descriptor to "00" -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_CoarseLargePageError1(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_CoarseLargePageError2 -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
and set the 2 LSB of 2nd level descriptor to "00" -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_CoarseLargePageError2(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_FineLargePageError1 -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
and set the 2 LSB of 1st level descriptor to "00" -
Write these descriptors into translation table -
SYNOPSYS : void MMU_FineLargePageError1(UWORD32 PA, -
UWORD32 VA, -
UWORD32 TTB, -
UWORD32 page_table_base, -
AP_t AP_bits) -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_FineLargePageError1(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_FineLargePage_Error2 -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
and set the 2 LSB of 2nd level descriptor to "00" -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_FineLargePage_Error2(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_CoarseSmallPageError1 -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
and set the 2 LSB of 1st level descriptor to "00" -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_CoarseSmallPageError1(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_CoarseSmallPageError2 -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
and set the 2 LSB of 2nd level descriptor to "00" -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_CoarseSmallPageError2(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_FineSmallPageError1 -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
and set the 2 LSB of 1st level descriptor to "00" -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_FineSmallPageError1(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_FineSmallPageError2 -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
and set the 2 LSB of 2nd level descriptor to "00" -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_FineSmallPageError2(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_FineTinyPageError1 -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
and set the 2 LSB of 1st level descriptor to "00" -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_FineTinyPageError1(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_FineTinyPageError2 -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
and set the 2 LSB of 2nd level descriptor to "00" -
Write these descriptors into translation table -
SYNOPSYS : void MMU_FineTinyPageError2(UWORD32 PA, -
UWORD32 VA, -
UWORD32 TTB, -
UWORD32 page_table_base, -
AP_t AP_bits) -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_FineTinyPageError2(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_WriteTlbEntry -
DESCRIPTION : To load one item in the TLB, 5 consecutive rhea register -
accesses are required. -
This entry is loaded at the address pointed by the lock -
counter register. -
1. Write CAM msb in CAM_REG_H register -
2. Write CAM lsb in CAM_REG_L register -
3. Write RAM msb in RAM_REG_H register -
4. Write RAM lsb in RAM_REG_L register -
5. Update Lock Counter register -
6. Write 1 in LD_TLB_REG register -
PARAMETERS : mmu_name could be DSP_MMU -
LB_MMU -
HSAB_MMU -
physical_address -
virtual_address -
slst could be SECTION -
LARGE_PAGE -
SMALL_PAGE -
TINT_PAGE -
AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
locked_base_value -
current_entry -
p_bit could be ENTRY_NOT_PRESERVED -
ENTRY_PRESERVED -
RETURN VALUE: None. -
LIMITATIONS : It is possible to load an entry in the TLB only if -
the WTL is DISABLED. -
-----------------------------------------------------------------------------
*/
void MMU_WriteTlbEntry(MMU_NAME_t mmu_name,
UWORD32 physical_address,
UWORD32 virtual_address,
SLST_t slst_bit,
AP_t ap_bits,
UWORD8 locked_base_value, // between 0 and 31
UWORD8 current_entry, // between base_value and 31
PRESERVED_t p_bit);
#endif
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