📄 mmu.h
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PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
ap_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define Set_RAM_Entry(mmu_name, physical_address, ap_bits) \
{ \
switch(mmu_name) \
{ \
case HSAB_MMU : \
{ \
RAM_H_REG_HSAB = (physical_address >> 16); \
RAM_L_REG_HSAB = ((ap_bits << 8) | (physical_address & 0x0000FC00)); \
break; \
} \
case LB_MMU : \
{ \
RAM_H_REG_LOCAL_BUS = (physical_address >> 16); \
RAM_L_REG_LOCAL_BUS = ((ap_bits << 8) | \
(physical_address & 0x0000FC00)); break; \
} \
case DSP_MMU : \
{ \
RAM_H_REG_DSP = (physical_address >> 16); \
RAM_L_REG_DSP = ((ap_bits << 8) | (physical_address & 0x0000FC00)); \
break; \
} \
} \
}
/*
-----------------------------------------------------------------------------
NAME : MMU_CheckRamEntry
DESCRIPTION : check if RAM entry low and high register
are well written according to parameters
PARAMETERS : - mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
- physical_address,
- ap_bits could be NOT_ACCESSIBLE
READ_ONLY
FULL_ACCESS
RETURN VALUE: 0 if ok else 4 if error on ERROR_RAM_H_REG
8 if error on ERROR_RAM_L_REG
12 if error on ERROR_RAM_L_REG and ERROR_RAM_H_REG
LIMITATIONS : None.
-----------------------------------------------------------------------------
*/
UWORD16 MMU_CheckRamEntry(MMU_NAME_t mmu_name,
UWORD32 physical_address,
AP_t ap_bits);
/*
-----------------------------------------------------------------------------
NAME : Load_Entry_In_TLB -
DESCRIPTION : Write 1 in LD_TLB_REG -
SYNOPSYS : void Load_Entry_In_TLB (MMU_NAME_t mmu_name) -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define Load_Entry_In_TLB(mmu_name) \
{ \
switch(mmu_name) \
{ \
case HSAB_MMU : \
{ \
LD_TLB_REG_HSAB = 1; break; \
} \
case LB_MMU : \
{ \
LD_TLB_REG_LOCAL_BUS = 1; break; \
} \
case DSP_MMU : \
{ \
LD_TLB_REG_DSP = 1; break; \
} \
} \
}
/*
-----------------------------------------------------------------------------
NAME : Read_Entry_In_TLB -
DESCRIPTION : Write 2 in LD_TLB_REG -
SYNOPSYS : void Read_Entry_In_TLB (MMU_NAME_t mmu_name) -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define Read_Entry_In_TLB(mmu_name) \
{ \
switch(mmu_name) \
{ \
case HSAB_MMU : \
{ \
LD_TLB_REG_HSAB = 2; break; \
} \
case LB_MMU : \
{ \
LD_TLB_REG_LOCAL_BUS = 2; break; \
} \
case DSP_MMU : \
{ \
LD_TLB_REG_DSP = 2; break; \
} \
} \
}
/*
-----------------------------------------------------------------------------
NAME : MMU_ReadLockCounter -
DESCRIPTION : Read Lock Counter Register -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: read value -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
UWORD16 MMU_ReadLockCounter(MMU_NAME_t);
/*
-----------------------------------------------------------------------------
NAME : MMU_ReadBaseValue -
DESCRIPTION : Read Base Value (locked entries) -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: Base Value -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
UWORD8 MMU_ReadBaseValue(MMU_NAME_t);
/*
-----------------------------------------------------------------------------
NAME : MMU_ReadCurrentVictim -
DESCRIPTION : Read Current Victim = Current entry pointed by the WTL -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: Current Victim -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
UWORD8 MMU_ReadCurrentVictim(MMU_NAME_t);
/*
-----------------------------------------------------------------------------
NAME : MMU_ReadCamEntry -
DESCRIPTION : Read CAM_H_REG and CAM_L_REG Registers -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: CAM Value -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
UWORD32 MMU_ReadCamEntry(MMU_NAME_t);
/*
-----------------------------------------------------------------------------
NAME : MMU_IsCamEntryValid -
DESCRIPTION : Check Valid bif of CAM_L_REG Register -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: CAM Value -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
BOOL MMU_IsCamEntryValid(MMU_NAME_t);
/*
-----------------------------------------------------------------------------
NAME : MMU_ReadRamEntry -
DESCRIPTION : Read RAM_H_REG and RAM_L_REG Registers -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: RAM Value -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
UWORD32 MMU_ReadRamEntry(MMU_NAME_t);
/*
-----------------------------------------------------------------------------
NAME : Global_Flush -
DESCRIPTION : Flush all the non-protected TLB entries -
SYNOPSYS : void Global_Flush (MMU_NAME_t mmu_name) -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define Global_Flush(mmu_name) \
{ \
switch(mmu_name) \
{ \
case HSAB_MMU : \
{ \
GFLUSH_REG_HSAB = 1; break; \
} \
case LB_MMU : \
{ \
GFLUSH_REG_LOCAL_BUS = 1; break; \
} \
case DSP_MMU : \
{ \
GFLUSH_REG_DSP = 1; break; \
} \
} \
}
/*
-----------------------------------------------------------------------------
NAME : Flush_Entry -
DESCRIPTION : Flush the TLB entry pointed by the lock counter register -
even if this entry is set protected -
SYNOPSYS : void Flush_Entry (MMU_NAME_t mmu_name) -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define Flush_Entry(mmu_name) \
{ \
switch(mmu_name) \
{ \
case HSAB_MMU : \
{ \
FLUSH_ENTRY_REG_HSAB = 1; break; \
} \
case LB_MMU : \
{ \
FLUSH_ENTRY_REG_LOCAL_BUS = 1; break; \
} \
case DSP_MMU : \
{ \
FLUSH_ENTRY_REG_DSP = 1; break; \
} \
} \
}
/*
-----------------------------------------------------------------------------
NAME : MMU_Section -
DESCRIPTION : Build 1st level descriptor and address of this descriptor -
Write this descriptor into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_Section (MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_CoarseLargePage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_CoarseLargePage(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_FineLargePage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_FineLargePage(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
/*
-----------------------------------------------------------------------------
NAME : MMU_CoarseSmallPage -
DESCRIPTION : Build 1st & 2nd level descriptors and addresses -
Write these descriptors into translation table -
PARAMETERS : AP_bits could be NOT_ACCESSIBLE -
READ_ONLY -
FULL_ACCESS -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
void MMU_CoarseSmallPage(MMU_NAME_t mmu_name,
UWORD32 PA,
UWORD32 VA,
UWORD32 TTB,
UWORD32 page_table_base,
AP_t AP_bits);
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