📄 mmu.h
字号:
//===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved.
//
// Description : Header file for the MMUs (local Bus and Modem)
//
// Project : OMAP3
//
// FUNCTIONS PROVIDED :
// Is_WTL_working
//
// MMU_ReadFaultAddress
// MMU_ReadFaultStatus
//
// MMU_ReadTtb
//
//Modified by Tom Shepherd: MMU_ReadCamEntry
//Modified by Tom Shepherd: MMU_ReadRamEntry
//
// MMU_ReadLockCounter
//
//
// MACROS PROVIDED :
// Reset_MMU
// Release_Reset_MMU
// Enable_MMU
// Disable_MMU
// Enable_WTL
// Disable_WTL
//
// Acknowledge_IT
//
// Set_TTB
//
// Load_Entry_In_TLB
//
//Added by Tom Shepherd: Read_Entry_In_TLB
//
// Set_CAM_Entry
// MMU_IsCamEntryValid
// Set_RAM_Entry
// Update_Lock_Counter
//
// Global_Flush
// Flush_entry
//
// TRANSLATION TABLE FUNCTION PROVIDED:
//
// MMU_Section
// MMU_Section_Error1
// MMU_CoarseLargePage
// MMU_CoarseLargePageError1
// MMU_CoarseLargePageError2
// MMU_FineLargePage
// MMU_FineLargePageError1
// MMU_FineLargePage_Error2
// MMU_CoarseSmallPage
// MMU_CoarseSmallPageError1
// MMU_CoarseSmallPageError2
// MMU_Fine_SmallPage
// MMU_Fine_SmallPage_Error1
// MMU_Fine_SmallPage_Error2
// MMU_Fine_TinyPage
// MMU_Fine_TinyPage_Error1
// MMU_Fine_TinyPage_Error2
//
// MMU_WriteTlbEntry
//
//===============================================================================
#ifndef _MMU__HH
#define _MMU__HH
#include "global_types.h"
#include "mem.h"
#define WALKING_ST_REG_OFFSET 0x04
#define CNTL_REG_OFFSET 0x08
#define FAULT_AD_H_REG_OFFSET 0x0C
#define FAULT_AD_L_REG_OFFSET 0x10
#define FAULT_ST_REG_OFFSET 0x14
#define IT_ACK_REG_OFFSET 0x18
#define TTB_H_REG_OFFSET 0x1C
#define TTB_L_REG_OFFSET 0x20
#define LOCK_REG_OFFSET 0x24
#define LD_TLB_REG_OFFSET 0x28
#define CAM_H_REG_OFFSET 0x2C
#define CAM_L_REG_OFFSET 0x30
#define RAM_H_REG_OFFSET 0x34
#define RAM_L_REG_OFFSET 0x38
#define GFLUSH_REG_OFFSET 0x3C
#define FLUSH_ENTRY_REG_OFFSET 0x40
#define READ_CAM_H_REG_OFFSET 0x44
#define READ_CAM_L_REG_OFFSET 0x48
#define READ_RAM_H_REG_OFFSET 0x4C
#define READ_RAM_L_REG_OFFSET 0x50
#define IDLE_CTRL_REG_OFFSET 0x54
#define MMU_PROTECT_OFFSET 0x58
#define WALKING_ST_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + WALKING_ST_REG_OFFSET))
#define CNTL_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + CNTL_REG_OFFSET))
#define FAULT_AD_H_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + FAULT_AD_H_REG_OFFSET))
#define FAULT_AD_L_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + FAULT_AD_L_REG_OFFSET))
#define FAULT_ST_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + FAULT_ST_REG_OFFSET))
#define IT_ACK_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + IT_ACK_REG_OFFSET))
#define TTB_H_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + TTB_H_REG_OFFSET))
#define TTB_L_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + TTB_L_REG_OFFSET))
#define LOCK_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + LOCK_REG_OFFSET))
#define LD_TLB_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + LD_TLB_REG_OFFSET))
#define CAM_H_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + CAM_H_REG_OFFSET))
#define CAM_L_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + CAM_L_REG_OFFSET))
#define RAM_H_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + RAM_H_REG_OFFSET))
#define RAM_L_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + RAM_L_REG_OFFSET))
#define GFLUSH_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + GFLUSH_REG_OFFSET))
#define FLUSH_ENTRY_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + FLUSH_ENTRY_REG_OFFSET))
#define READ_CAM_H_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + READ_CAM_H_REG_OFFSET))
#define READ_CAM_L_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + READ_CAM_L_REG_OFFSET))
#define READ_RAM_H_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + READ_RAM_H_REG_OFFSET))
#define READ_RAM_L_REG_HSAB \
REG32((MEM_HSAB_MMU_SUPERVISOR_ADDR + READ_RAM_L_REG_OFFSET))
#define WALKING_ST_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + WALKING_ST_REG_OFFSET))
#define CNTL_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + CNTL_REG_OFFSET))
#define FAULT_AD_H_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + FAULT_AD_H_REG_OFFSET))
#define FAULT_AD_L_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + FAULT_AD_L_REG_OFFSET))
#define FAULT_ST_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + FAULT_ST_REG_OFFSET))
#define IT_ACK_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + IT_ACK_REG_OFFSET))
#define TTB_H_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + TTB_H_REG_OFFSET))
#define TTB_L_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + TTB_L_REG_OFFSET))
#define LOCK_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + LOCK_REG_OFFSET))
#define LD_TLB_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + LD_TLB_REG_OFFSET))
#define CAM_H_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + CAM_H_REG_OFFSET))
#define CAM_L_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + CAM_L_REG_OFFSET))
#define RAM_H_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + RAM_H_REG_OFFSET))
#define RAM_L_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + RAM_L_REG_OFFSET))
#define GFLUSH_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + GFLUSH_REG_OFFSET))
#define FLUSH_ENTRY_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + FLUSH_ENTRY_REG_OFFSET))
#define READ_CAM_H_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + READ_CAM_H_REG_OFFSET))
#define READ_CAM_L_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + READ_CAM_L_REG_OFFSET))
#define READ_RAM_H_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + READ_RAM_H_REG_OFFSET))
#define READ_RAM_L_REG_LOCAL_BUS \
REG32((MEM_LOCAL_BUS_MMU_SUPERVISOR_ADDR + READ_RAM_L_REG_OFFSET))
#define WALKING_ST_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + WALKING_ST_REG_OFFSET))
#define CNTL_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + CNTL_REG_OFFSET))
#define FAULT_AD_H_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + FAULT_AD_H_REG_OFFSET))
#define FAULT_AD_L_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + FAULT_AD_L_REG_OFFSET))
#define FAULT_ST_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + FAULT_ST_REG_OFFSET))
#define IT_ACK_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + IT_ACK_REG_OFFSET))
#define TTB_H_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + TTB_H_REG_OFFSET))
#define TTB_L_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + TTB_L_REG_OFFSET))
#define LOCK_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + LOCK_REG_OFFSET))
#define LD_TLB_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + LD_TLB_REG_OFFSET))
#define CAM_H_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + CAM_H_REG_OFFSET))
#define CAM_L_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + CAM_L_REG_OFFSET))
#define RAM_H_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + RAM_H_REG_OFFSET))
#define RAM_L_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + RAM_L_REG_OFFSET))
#define GFLUSH_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + GFLUSH_REG_OFFSET))
#define FLUSH_ENTRY_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + FLUSH_ENTRY_REG_OFFSET))
#define READ_CAM_H_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + READ_CAM_H_REG_OFFSET))
#define READ_CAM_L_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + READ_CAM_L_REG_OFFSET))
#define READ_RAM_H_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + READ_RAM_H_REG_OFFSET))
#define READ_RAM_L_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + READ_RAM_L_REG_OFFSET))
#define MMU_PROTECT_REG_DSP \
REG32((MEM_DSP_MMU_SUPERVISOR_ADDR + MMU_PROTECT_OFFSET))
// Walking_st_reg
#define WTL_WORKING_MASK 0x0002
#define PREFETCH_WORKING_MASK 0x0001 // Not used !
// Control Register
#define RESET_SW_MMU_MASK 0x0001
#define MMU_ENABLE_MASK 0x0002
#define WTL_ENABLE_MASK 0x0004
#define STREAMING_BUFF_EN_MASK 0x0010 // Not used !
#define ENDIANISM_EN_MASK 0x0020 // Not used !
#define BURST_16MNGT_EN_MASK 0x0040 // Not used !
// IT Acknowledge Register
#define IT_ACK_MASK 0x0001
typedef enum { DSP_MMU, LB_MMU, HSAB_MMU } MMU_NAME_t;
typedef enum { TRANS_FAULT = 1, TLB_MISS = 2,
PERM_FAULT = 4, PREFETCH_ERR = 8 } FAULT_STATUS_t;
typedef enum { SECTION = 0, LARGE_PAGE = 1,
SMALL_PAGE = 2, TINY_PAGE = 3 } SLST_t;
typedef enum { NOT_ACCESSIBLE=0, READ_ONLY = 2, FULL_ACCESS = 3 } AP_t;
typedef enum { ENTRY_NOT_PRESERVED = 0, ENTRY_PRESERVED = 1 } PRESERVED_t;
/*
-----------------------------------------------------------------------------
NAME : MMU_IsWtlWorking -
DESCRIPTION : Check if the walking table is running -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: True if walking table is running, False if not. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
BOOL MMU_IsWtlWorking(MMU_NAME_t);
/*
-----------------------------------------------------------------------------
NAME : Reset_MMU -
DESCRIPTION : Resets the module. The module comes back to default config -
SYNOPSYS : void Reset_MMU (MMU_NAME_t mmu_name) -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define Reset_MMU(mmu_name) \
{ \
switch(mmu_name) \
{ \
case HSAB_MMU : \
{ \
ClearBit(CNTL_REG_HSAB,RESET_SW_MMU_MASK); break; \
} \
case LB_MMU : \
{ \
ClearBit(CNTL_REG_LOCAL_BUS,RESET_SW_MMU_MASK); break; \
} \
case DSP_MMU : \
{ \
ClearBit(CNTL_REG_DSP,RESET_SW_MMU_MASK); break; \
} \
} \
}
/*
-----------------------------------------------------------------------------
NAME : Release_Reset_MMU -
DESCRIPTION : Release Reset of module. -
SYNOPSYS : void Release_Reset_MMU (MMU_NAME_t mmu_name) -
PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU -
RETURN VALUE: None. -
LIMITATIONS : None. -
-----------------------------------------------------------------------------
*/
#define Release_Reset_MMU(mmu_name) \
{ \
switch(mmu_name) \
{ \
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -