icr_a9.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Filename             : icr.h

   Description          : Header file for the Intersystem Communication Register

   Project              : Perseus

   Author               : Sebastien Sabatier

   MACROS PROVIDED      :
                         icr_set_m_ctl
                         icr_release_gsm_reset
                         icr_reset_gsm
                         icr_set_pm_ba
                         icr_set_dm_ba
                         icr_set_rm_ba

                         icr_set_m_icr_flag
                         icr_reset_g_icr_flag
   
 FUNCTIONS PROVIDED    :
                         ICR_ReadMCtl
                         ICR_ReadGCtl
                         ICR_ReadPmBa
                         ICR_ReadDmBa
                         ICR_ReadRmBa

                         ICR_ReadMIcr
                         ICR_ReadGIcr

===============================================================================
*/
#ifndef _ICR__HH
#define _ICR__HH

#include "global_types.h"
#include "mapping.h"

#define M_ICR_REG_OFFSET 0x000
#define G_ICR_REG_OFFSET 0x002
#define M_CTL_REG_OFFSET 0x004
#define G_CTL_REG_OFFSET 0x006
#define PM_BA_REG_OFFSET 0x00A
#define DM_BA_REG_OFFSET 0x00C
#define RM_BA_REG_OFFSET 0x00E
#define PROTECT_REG_OFFSET 0x010
#define SSPI_TAS_OFFSET  0x012
#define DPRAM_OFFSET     0x400

#define M_ICR_REG_ADDR  (ICR_BASE_ADDR + M_ICR_REG_OFFSET)
#define G_ICR_REG_ADDR  (ICR_BASE_ADDR + G_ICR_REG_OFFSET)
#define M_CTL_REG_ADDR  (ICR_BASE_ADDR + M_CTL_REG_OFFSET)
#define G_CTL_REG_ADDR  (ICR_BASE_ADDR + G_CTL_REG_OFFSET)
#define PM_BA_REG_ADDR  (ICR_BASE_ADDR + PM_BA_REG_OFFSET)
#define DM_BA_REG_ADDR  (ICR_BASE_ADDR + DM_BA_REG_OFFSET)
#define RM_BA_REG_ADDR  (ICR_BASE_ADDR + RM_BA_REG_OFFSET)
#define PROTECT_REG_ADDR (ICR_BASE_ADDR + PROTECT_REG_OFFSET)
#define DPRAM_ADDR      (ICR_BASE_ADDR + DPRAM_OFFSET)
#define SSPI_TAS_ADDR   (ICR_BASE_ADDR + SSPI_TAS_OFFSET)

#define SIZE_OF_DPRAM_16BIT 16  // 320 in nominal mode, 16 in test mode

#define GSM_RST_MASK        0x0001

typedef enum { SIZE_64K = 0,  SIZE_128K = 1,
               SIZE_256K = 2, SIZE_512K = 3,
               SIZE_1M = 4,   SIZE_2M = 5,
               SIZE_4M = 6,   SIZE_8M = 7  } block_size_t;

typedef enum { RESET_GSM_S = 0, RELEASE_GSM_RESET = 1 } reset_t;

typedef enum { NO_ICR_INTEN = 0, ICR_INTEN = 1 } icr_inten_t;

  /*
-----------------------------------------------------------------------------
 NAME        : icr_set_m_ctl                                                -
 DESCRIPTION : Set the MPU-S Control register                               -
 SYNOPSYS    : void icr_set_m_ctl(reset_t gsm_rst,                          -
                                  block_size_t pgm_blk_size,                -
                                  block_size_t data_blk_size,               -
                                  block_size_t rand_blk_size,               -
                                  icr_inten_t m_icr_inten,                  -
                                  icr_inten_t g_icr_inten)                  -
 PARAMETERS  : See Intersystem Communication Register Specification         -
 RETURN VALUE: None.                                                        -
 LIMITATIONS : None.                                                        -
-----------------------------------------------------------------------------
*/ 
#define icr_set_m_ctl(gsm_rst, pgm_blk_size, data_blk_size, rand_blk_size,\
                      m_icr_inten, g_icr_inten) \
{ \
  *(UWORD16*)M_CTL_REG_ADDR = \
    ( gsm_rst | (pgm_blk_size << 1) | (data_blk_size << 4) | \
      (rand_blk_size << 7) | (m_icr_inten << 10) | (g_icr_inten << 11) ); \
}

  /*
-----------------------------------------------------------------------------
 NAME        : icr_release_gsm_reset                                        -
 DESCRIPTION : Set the MPU-S Control register bit 0 to 0 (reset GSM_S)      -
               and then Set the MPU_S Control register bit 0 to 1           -
               (release GSM_S's reset)                                      -
 SYNOPSYS    : void icr_release_gsm_reset (void)                            -
 PARAMETERS  : None.                                                        -
 RETURN VALUE: None.                                                        -
 LIMITATIONS : None.                                                        -
-----------------------------------------------------------------------------
*/ 
#define icr_release_gsm_reset() \
{ \
UWORD16 value; \
 value = *(UWORD16*)M_CTL_REG_ADDR; \
\
  *(UWORD16*)M_CTL_REG_ADDR = ( value & ~GSM_RST_MASK ); \
  *(UWORD16*)M_CTL_REG_ADDR = ( value | RELEASE_GSM_RESET ); \
}

  /*
-----------------------------------------------------------------------------
 NAME        : icr_reset_gsm                                                -
 DESCRIPTION : Set the MPU-S Control register bit 0 to 0                    -
 SYNOPSYS    : void icr_reset_gsm (void)                                    -
 PARAMETERS  : None.                                                        -
 RETURN VALUE: None.                                                        -
 LIMITATIONS : None.                                                        -
-----------------------------------------------------------------------------
*/ 
#define icr_reset_gsm() \
{ \
UWORD16 value; \
 value = *(UWORD16*)M_CTL_REG_ADDR; \
\
  *(UWORD16*)M_CTL_REG_ADDR = \
    ( value & ~GSM_RST_MASK ); \
}

  /*
-----------------------------------------------------------------------------
 NAME        : icr_force_gsm_reset                                          -
 DESCRIPTION : Set the MPU-S Control register bit 0 to 1                    -
 SYNOPSYS    : void icr_force_gsm_reset (void)                              -
 PARAMETERS  : None.                                                        -
 RETURN VALUE: None.                                                        -
 LIMITATIONS : None.                                                        -
-----------------------------------------------------------------------------
*/ 
#define icr_force_gsm_reset() \
{ \
UWORD16 value; \
 value = *(UWORD16*)M_CTL_REG_ADDR; \
\
  *(UWORD16*)M_CTL_REG_ADDR = ( value | RELEASE_GSM_RESET ); \
}

/*
-----------------------------------------------------------------------------
 NAME        : ICR_ReadMCtl                                               -
 DESCRIPTION : Read the MPU-S Control Register                              -
 PARAMETERS  : None.                                                        -
 RETURN VALUE: Read value.                                                  -
 LIMITATIONS : None.                                                        -
-----------------------------------------------------------------------------
*/ 
UWORD16 ICR_ReadMCtl (void);

/*
-----------------------------------------------------------------------------
 NAME        : ICR_ReadGCtl                                               -