📄 elcd.h
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#define ELCD_CYCLE1_REG4_CYCLE1_19_NUMB 5
#define ELCD_CYCLE1_REG4_CYCLE1_19_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG4_CYCLE1_18_STS_POS 23
#define ELCD_CYCLE1_REG4_CYCLE1_18_STS_NUMB 1
#define ELCD_CYCLE1_REG4_CYCLE1_18_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG4_CYCLE1_18_POS 18
#define ELCD_CYCLE1_REG4_CYCLE1_18_NUMB 5
#define ELCD_CYCLE1_REG4_CYCLE1_18_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG4_CYCLE1_17_STS_POS 17
#define ELCD_CYCLE1_REG4_CYCLE1_17_STS_NUMB 1
#define ELCD_CYCLE1_REG4_CYCLE1_17_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG4_CYCLE1_17_POS 12
#define ELCD_CYCLE1_REG4_CYCLE1_17_NUMB 5
#define ELCD_CYCLE1_REG4_CYCLE1_17_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG4_CYCLE1_16_STS_POS 11
#define ELCD_CYCLE1_REG4_CYCLE1_16_STS_NUMB 1
#define ELCD_CYCLE1_REG4_CYCLE1_16_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG4_CYCLE1_16_POS 6
#define ELCD_CYCLE1_REG4_CYCLE1_16_NUMB 5
#define ELCD_CYCLE1_REG4_CYCLE1_16_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG4_CYCLE1_15_STS_POS 5
#define ELCD_CYCLE1_REG4_CYCLE1_15_STS_NUMB 1
#define ELCD_CYCLE1_REG4_CYCLE1_15_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG4_CYCLE1_15_POS 0
#define ELCD_CYCLE1_REG4_CYCLE1_15_NUMB 5
#define ELCD_CYCLE1_REG4_CYCLE1_15_RES_VAL 0x0
//R/W
//ELCD_CYCLE1_REG5
//-------------------
#define ELCD_CYCLE1_REG5 REG32(ELCD_BASE_ADDR_ARM+ELCD_CYCLE1_REG5_OFFSET)
#define ELCD_CYCLE1_REG5_RESERVED_POS 24
#define ELCD_CYCLE1_REG5_RESERVED_NUMB 8
#define ELCD_CYCLE1_REG5_RESERVED_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG5_CYCLE1_23_STS_POS 23
#define ELCD_CYCLE1_REG5_CYCLE1_23_STS_NUMB 1
#define ELCD_CYCLE1_REG5_CYCLE1_23_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG5_CYCLE1_23_POS 18
#define ELCD_CYCLE1_REG5_CYCLE1_23_NUMB 5
#define ELCD_CYCLE1_REG5_CYCLE1_23_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG5_CYCLE1_22_STS_POS 17
#define ELCD_CYCLE1_REG5_CYCLE1_22_STS_NUMB 1
#define ELCD_CYCLE1_REG5_CYCLE1_22_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG5_CYCLE1_22_POS 12
#define ELCD_CYCLE1_REG5_CYCLE1_22_NUMB 5
#define ELCD_CYCLE1_REG5_CYCLE1_22_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG5_CYCLE1_21_STS_POS 11
#define ELCD_CYCLE1_REG5_CYCLE1_21_STS_NUMB 1
#define ELCD_CYCLE1_REG5_CYCLE1_21_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG5_CYCLE1_21_POS 6
#define ELCD_CYCLE1_REG5_CYCLE1_21_NUMB 5
#define ELCD_CYCLE1_REG5_CYCLE1_21_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG5_CYCLE1_20_STS_POS 5
#define ELCD_CYCLE1_REG5_CYCLE1_20_STS_NUMB 1
#define ELCD_CYCLE1_REG5_CYCLE1_20_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG5_CYCLE1_20_POS 0
#define ELCD_CYCLE1_REG5_CYCLE1_20_NUMB 5
#define ELCD_CYCLE1_REG5_CYCLE1_20_RES_VAL 0x0
//R/W
//ELCD_CYCLE2_REG1
//-------------------
#define ELCD_CYCLE2_REG1 REG32(ELCD_BASE_ADDR_ARM+ELCD_CYCLE2_REG1_OFFSET)
#define ELCD_CYCLE2_REG1_RESERVED_POS 30
#define ELCD_CYCLE2_REG1_RESERVED_NUMB 2
#define ELCD_CYCLE2_REG1_RESERVED_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG1_CYCLE2_4_STS_POS 29
#define ELCD_CYCLE2_REG1_CYCLE2_4_STS_NUMB 1
#define ELCD_CYCLE2_REG1_CYCLE2_4_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG1_CYCLE2_4_POS 24
#define ELCD_CYCLE2_REG1_CYCLE2_4_NUMB 5
#define ELCD_CYCLE2_REG1_CYCLE2_4_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG1_CYCLE2_3_STS_POS 23
#define ELCD_CYCLE2_REG1_CYCLE2_3_STS_NUMB 1
#define ELCD_CYCLE2_REG1_CYCLE2_3_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG1_CYCLE2_3_POS 18
#define ELCD_CYCLE2_REG1_CYCLE2_3_NUMB 5
#define ELCD_CYCLE2_REG1_CYCLE2_3_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG1_CYCLE2_2_STS_POS 17
#define ELCD_CYCLE2_REG1_CYCLE2_2_STS_NUMB 1
#define ELCD_CYCLE2_REG1_CYCLE2_2_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG1_CYCLE2_2_POS 12
#define ELCD_CYCLE2_REG1_CYCLE2_2_NUMB 5
#define ELCD_CYCLE2_REG1_CYCLE2_2_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG1_CYCLE2_1_STS_POS 11
#define ELCD_CYCLE2_REG1_CYCLE2_1_STS_NUMB 1
#define ELCD_CYCLE2_REG1_CYCLE2_1_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG1_CYCLE2_1_POS 6
#define ELCD_CYCLE2_REG1_CYCLE2_1_NUMB 5
#define ELCD_CYCLE2_REG1_CYCLE2_1_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG1_CYCLE2_0_STS_POS 5
#define ELCD_CYCLE2_REG1_CYCLE2_0_STS_NUMB 1
#define ELCD_CYCLE2_REG1_CYCLE2_0_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG1_CYCLE2_0_POS 0
#define ELCD_CYCLE2_REG1_CYCLE2_0_NUMB 5
#define ELCD_CYCLE2_REG1_CYCLE2_0_RES_VAL 0x0
//R/W
//ELCD_CYCLE2_REG2
//-------------------
#define ELCD_CYCLE2_REG2 REG32(ELCD_BASE_ADDR_ARM+ELCD_CYCLE2_REG2_OFFSET)
#define ELCD_CYCLE2_REG2_RESERVED_POS 30
#define ELCD_CYCLE2_REG2_RESERVED_NUMB 2
#define ELCD_CYCLE2_REG2_RESERVED_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG2_CYCLE2_9_STS_POS 29
#define ELCD_CYCLE2_REG2_CYCLE2_9_STS_NUMB 1
#define ELCD_CYCLE2_REG2_CYCLE2_9_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG2_CYCLE2_9_POS 24
#define ELCD_CYCLE2_REG2_CYCLE2_9_NUMB 5
#define ELCD_CYCLE2_REG2_CYCLE2_9_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG2_CYCLE2_8_STS_POS 23
#define ELCD_CYCLE2_REG2_CYCLE2_8_STS_NUMB 1
#define ELCD_CYCLE2_REG2_CYCLE2_8_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG2_CYCLE2_8_POS 18
#define ELCD_CYCLE2_REG2_CYCLE2_8_NUMB 5
#define ELCD_CYCLE2_REG2_CYCLE2_8_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG2_CYCLE2_7_STS_POS 17
#define ELCD_CYCLE2_REG2_CYCLE2_7_STS_NUMB 1
#define ELCD_CYCLE2_REG2_CYCLE2_7_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG2_CYCLE2_7_POS 12
#define ELCD_CYCLE2_REG2_CYCLE2_7_NUMB 5
#define ELCD_CYCLE2_REG2_CYCLE2_7_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG2_CYCLE2_6_STS_POS 11
#define ELCD_CYCLE2_REG2_CYCLE2_6_STS_NUMB 1
#define ELCD_CYCLE2_REG2_CYCLE2_6_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG2_CYCLE2_6_POS 6
#define ELCD_CYCLE2_REG2_CYCLE2_6_NUMB 5
#define ELCD_CYCLE2_REG2_CYCLE2_6_RES_VAL 0x0
//R/W
#define ELCD_CYCLE2_REG2_CYCLE2_5_STS_POS 5
#define ELCD_CYCLE2_REG2_CYCLE2_5_STS_NUMB 1
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