📄 elcd.h
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#define ELCD_PIXELPOS_REG_PIX2_RP_POS 5
#define ELCD_PIXELPOS_REG_PIX2_RP_NUMB 5
#define ELCD_PIXELPOS_REG_PIX2_RP_RES_VAL 0x0
//R/W
#define ELCD_PIXELPOS_REG_PIX1_RP_POS 0
#define ELCD_PIXELPOS_REG_PIX1_RP_NUMB 5
#define ELCD_PIXELPOS_REG_PIX1_RP_RES_VAL 0x0
//R/W
//ELCD_CYCLE1_REG1
//-------------------
#define ELCD_CYCLE1_REG1 REG32(ELCD_BASE_ADDR_ARM+ELCD_CYCLE1_REG1_OFFSET)
#define ELCD_CYCLE1_REG1_RESERVED_POS 30
#define ELCD_CYCLE1_REG1_RESERVED_NUMB 2
#define ELCD_CYCLE1_REG1_RESERVED_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG1_CYCLE1_4_STS_POS 29
#define ELCD_CYCLE1_REG1_CYCLE1_4_STS_NUMB 1
#define ELCD_CYCLE1_REG1_CYCLE1_4_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG1_CYCLE1_4_POS 24
#define ELCD_CYCLE1_REG1_CYCLE1_4_NUMB 5
#define ELCD_CYCLE1_REG1_CYCLE1_4_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG1_CYCLE1_3_STS_POS 23
#define ELCD_CYCLE1_REG1_CYCLE1_3_STS_NUMB 1
#define ELCD_CYCLE1_REG1_CYCLE1_3_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG1_CYCLE1_3_POS 18
#define ELCD_CYCLE1_REG1_CYCLE1_3_NUMB 5
#define ELCD_CYCLE1_REG1_CYCLE1_3_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG1_CYCLE1_2_STS_POS 17
#define ELCD_CYCLE1_REG1_CYCLE1_2_STS_NUMB 1
#define ELCD_CYCLE1_REG1_CYCLE1_2_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG1_CYCLE1_2_POS 12
#define ELCD_CYCLE1_REG1_CYCLE1_2_NUMB 5
#define ELCD_CYCLE1_REG1_CYCLE1_2_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG1_CYCLE1_1_STS_POS 11
#define ELCD_CYCLE1_REG1_CYCLE1_1_STS_NUMB 1
#define ELCD_CYCLE1_REG1_CYCLE1_1_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG1_CYCLE1_1_POS 6
#define ELCD_CYCLE1_REG1_CYCLE1_1_NUMB 5
#define ELCD_CYCLE1_REG1_CYCLE1_1_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG1_CYCLE1_0_STS_POS 5
#define ELCD_CYCLE1_REG1_CYCLE1_0_STS_NUMB 1
#define ELCD_CYCLE1_REG1_CYCLE1_0_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG1_CYCLE1_0_POS 0
#define ELCD_CYCLE1_REG1_CYCLE1_0_NUMB 5
#define ELCD_CYCLE1_REG1_CYCLE1_0_RES_VAL 0x0
//R/W
//ELCD_CYCLE1_REG2
//-------------------
#define ELCD_CYCLE1_REG2 REG32(ELCD_BASE_ADDR_ARM+ELCD_CYCLE1_REG2_OFFSET)
#define ELCD_CYCLE1_REG2_RESERVED_POS 30
#define ELCD_CYCLE1_REG2_RESERVED_NUMB 2
#define ELCD_CYCLE1_REG2_RESERVED_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG2_CYCLE1_9_STS_POS 29
#define ELCD_CYCLE1_REG2_CYCLE1_9_STS_NUMB 1
#define ELCD_CYCLE1_REG2_CYCLE1_9_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG2_CYCLE1_9_POS 24
#define ELCD_CYCLE1_REG2_CYCLE1_9_NUMB 5
#define ELCD_CYCLE1_REG2_CYCLE1_9_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG2_CYCLE1_8_STS_POS 23
#define ELCD_CYCLE1_REG2_CYCLE1_8_STS_NUMB 1
#define ELCD_CYCLE1_REG2_CYCLE1_8_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG2_CYCLE1_8_POS 18
#define ELCD_CYCLE1_REG2_CYCLE1_8_NUMB 5
#define ELCD_CYCLE1_REG2_CYCLE1_8_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG2_CYCLE1_7_STS_POS 17
#define ELCD_CYCLE1_REG2_CYCLE1_7_STS_NUMB 1
#define ELCD_CYCLE1_REG2_CYCLE1_7_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG2_CYCLE1_7_POS 12
#define ELCD_CYCLE1_REG2_CYCLE1_7_NUMB 5
#define ELCD_CYCLE1_REG2_CYCLE1_7_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG2_CYCLE1_6_STS_POS 11
#define ELCD_CYCLE1_REG2_CYCLE1_6_STS_NUMB 1
#define ELCD_CYCLE1_REG2_CYCLE1_6_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG2_CYCLE1_6_POS 6
#define ELCD_CYCLE1_REG2_CYCLE1_6_NUMB 5
#define ELCD_CYCLE1_REG2_CYCLE1_6_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG2_CYCLE1_5_STS_POS 5
#define ELCD_CYCLE1_REG2_CYCLE1_5_STS_NUMB 1
#define ELCD_CYCLE1_REG2_CYCLE1_5_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG2_CYCLE1_5_POS 0
#define ELCD_CYCLE1_REG2_CYCLE1_5_NUMB 5
#define ELCD_CYCLE1_REG2_CYCLE1_5_RES_VAL 0x0
//R/W
//ELCD_CYCLE1_REG3
//-------------------
#define ELCD_CYCLE1_REG3 REG32(ELCD_BASE_ADDR_ARM+ELCD_CYCLE1_REG3_OFFSET)
#define ELCD_CYCLE1_REG3_RESERVED_POS 30
#define ELCD_CYCLE1_REG3_RESERVED_NUMB 2
#define ELCD_CYCLE1_REG3_RESERVED_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG3_CYCLE1_14_STS_POS 29
#define ELCD_CYCLE1_REG3_CYCLE1_14_STS_NUMB 1
#define ELCD_CYCLE1_REG3_CYCLE1_14_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG3_CYCLE1_14_POS 24
#define ELCD_CYCLE1_REG3_CYCLE1_14_NUMB 5
#define ELCD_CYCLE1_REG3_CYCLE1_14_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG3_CYCLE1_13_STS_POS 23
#define ELCD_CYCLE1_REG3_CYCLE1_13_STS_NUMB 1
#define ELCD_CYCLE1_REG3_CYCLE1_13_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG3_CYCLE1_13_POS 18
#define ELCD_CYCLE1_REG3_CYCLE1_13_NUMB 5
#define ELCD_CYCLE1_REG3_CYCLE1_13_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG3_CYCLE1_12_STS_POS 17
#define ELCD_CYCLE1_REG3_CYCLE1_12_STS_NUMB 1
#define ELCD_CYCLE1_REG3_CYCLE1_12_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG3_CYCLE1_12_POS 12
#define ELCD_CYCLE1_REG3_CYCLE1_12_NUMB 5
#define ELCD_CYCLE1_REG3_CYCLE1_12_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG3_CYCLE1_11_STS_POS 11
#define ELCD_CYCLE1_REG3_CYCLE1_11_STS_NUMB 1
#define ELCD_CYCLE1_REG3_CYCLE1_11_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG3_CYCLE1_11_POS 6
#define ELCD_CYCLE1_REG3_CYCLE1_11_NUMB 5
#define ELCD_CYCLE1_REG3_CYCLE1_11_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG3_CYCLE1_10_STS_POS 5
#define ELCD_CYCLE1_REG3_CYCLE1_10_STS_NUMB 1
#define ELCD_CYCLE1_REG3_CYCLE1_10_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG3_CYCLE1_10_POS 0
#define ELCD_CYCLE1_REG3_CYCLE1_10_NUMB 5
#define ELCD_CYCLE1_REG3_CYCLE1_10_RES_VAL 0x0
//R/W
//ELCD_CYCLE1_REG4
//-------------------
#define ELCD_CYCLE1_REG4 REG32(ELCD_BASE_ADDR_ARM+ELCD_CYCLE1_REG4_OFFSET)
#define ELCD_CYCLE1_REG4_RESERVED_POS 30
#define ELCD_CYCLE1_REG4_RESERVED_NUMB 2
#define ELCD_CYCLE1_REG4_RESERVED_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG4_CYCLE1_19_STS_POS 29
#define ELCD_CYCLE1_REG4_CYCLE1_19_STS_NUMB 1
#define ELCD_CYCLE1_REG4_CYCLE1_19_STS_RES_VAL 0x0
//R/W
#define ELCD_CYCLE1_REG4_CYCLE1_19_POS 24
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