dualmodetimer2.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*Header modified by DSP-CONVERT V1.01 Script on  Tue Aug 13 14:48:17 MEST 2002*/
//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :dualmodetimer2.h
//
//   Date of Module Modification:6/12/02
//   Date of Generation :4/25/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _DUALMODETIMER2__H
#define _DUALMODETIMER2__H

//BEGIN INC GENERATION
//--------------------------------------


#ifndef DSP_ADJUST              /* If DSP_ADJUST is not defined, we are using */
#define DSP_ADJUST              /* include file for ARM code, we do not need any */
#endif                          /* modufucations. If this file is used for DSP code, */

//Register Offset
//-------------------
#define coeff8_arm   1
#define coeff16_arm  1
#define coeff32_arm  1

//-------------------

#define            DUALMODETIMER2_TIDR_OFFSET                                                                          (0x00 DSP_ADJUST)
#define            DUALMODETIMER2_TIOCP_CFG_OFFSET                                                                     (0x10 DSP_ADJUST)
#define            DUALMODETIMER2_TISTAT_OFFSET                                                                        (0x14 DSP_ADJUST)
#define            DUALMODETIMER2_TISR_OFFSET                                                                          (0x18 DSP_ADJUST)
#define            DUALMODETIMER2_TIER_OFFSET                                                                          (0x1C DSP_ADJUST)
#define            DUALMODETIMER2_TWER_OFFSET                                                                          (0x20 DSP_ADJUST)
#define            DUALMODETIMER2_TCLR_OFFSET                                                                          (0x24 DSP_ADJUST)
#define            DUALMODETIMER2_TCRR_OFFSET                                                                          (0x28 DSP_ADJUST)
#define            DUALMODETIMER2_TLDR_OFFSET                                                                          (0x2C DSP_ADJUST)
#define            DUALMODETIMER2_TTGR_OFFSET                                                                          (0x30 DSP_ADJUST)
#define            DUALMODETIMER2_TWPS_OFFSET                                                                          (0x34 DSP_ADJUST)
#define            DUALMODETIMER2_TMAR_OFFSET                                                                          (0x38 DSP_ADJUST)
#define            DUALMODETIMER2_TCAR_OFFSET                                                                          (0x3C DSP_ADJUST)
#define            DUALMODETIMER2_TSICR_OFFSET                                                                         (0x40 DSP_ADJUST)


#ifndef DSP_ACCESS



//DUALMODETIMER2_TIDR

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            DUALMODETIMER2_TIDR_16_0                                                                            REG16(DUALMODETIMER2_BASE_ADDR_ARM+DUALMODETIMER2_TIDR_OFFSET*coeff16_arm+0)
#else
#define            DUALMODETIMER2_TIDR_16_0                                                                            REG16(DUALMODETIMER2_BASE_ADDR_DSP+DUALMODETIMER2_TIDR_OFFSET)
#endif


#define            DUALMODETIMER2_TIDR_16_0_TID_REV_POS                                                                  0
#define            DUALMODETIMER2_TIDR_16_0_TID_REV_NUMB                                                                 8
#define            DUALMODETIMER2_TIDR_16_0_TID_REV_RES_VAL                                                              0x20
//R



#ifndef DSP_ACCESS
#define            DUALMODETIMER2_TIDR_16_2                                                                            REG16(DUALMODETIMER2_BASE_ADDR_ARM+DUALMODETIMER2_TIDR_OFFSET*coeff16_arm+2)
#else
#define            DUALMODETIMER2_TIDR_16_2                                                                            REG16(DUALMODETIMER2_BASE_ADDR_DSP+DUALMODETIMER2_TIDR_OFFSET+1)
#endif


#define            DUALMODETIMER2_TIDR_16_2_TID_REV_POS                                                                  0
#define            DUALMODETIMER2_TIDR_16_2_TID_REV_NUMB                                                                 8
#define            DUALMODETIMER2_TIDR_16_2_TID_REV_RES_VAL                                                              0x20

#ifndef DSP_ACCESS

#define            DUALMODETIMER2_TIDR_32                                                                              REG32(DUALMODETIMER2_BASE_ADDR_ARM+DUALMODETIMER2_TIDR_OFFSET*coeff32_arm)


#define            DUALMODETIMER2_TIDR_32_TID_REV_POS                                                                    0
#define            DUALMODETIMER2_TIDR_32_TID_REV_NUMB                                                                   8
#define            DUALMODETIMER2_TIDR_32_TID_REV_RES_VAL                                                               0x13
//R


//DUALMODETIMER2_TIOCP_CFG

#endif /* DSP_ACCESS */


#ifndef DSP_ACCESS
#define            DUALMODETIMER2_TIOCP_CFG_16_0                                                                       REG16(DUALMODETIMER2_BASE_ADDR_ARM+DUALMODETIMER2_TIOCP_CFG_OFFSET*coeff16_arm+0)
#else
#define            DUALMODETIMER2_TIOCP_CFG_16_0                                                                       REG16(DUALMODETIMER2_BASE_ADDR_DSP+DUALMODETIMER2_TIOCP_CFG_OFFSET)
#endif


#define            DUALMODETIMER2_TIOCP_CFG_16_0_EMUFREE_POS                                                             5
#define            DUALMODETIMER2_TIOCP_CFG_16_0_EMUFREE_NUMB                                                            1
#define            DUALMODETIMER2_TIOCP_CFG_16_0_EMUFREE_RES_VAL                                                         0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_16_0_IDLEMODE_POS                                                            3
#define            DUALMODETIMER2_TIOCP_CFG_16_0_IDLEMODE_NUMB                                                           2
#define            DUALMODETIMER2_TIOCP_CFG_16_0_IDLEMODE_RES_VAL                                                        0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_16_0_ENAWAKEUP_POS                                                           2
#define            DUALMODETIMER2_TIOCP_CFG_16_0_ENAWAKEUP_NUMB                                                          1
#define            DUALMODETIMER2_TIOCP_CFG_16_0_ENAWAKEUP_RES_VAL                                                       0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_16_0_SOFTRESET_POS                                                           1
#define            DUALMODETIMER2_TIOCP_CFG_16_0_SOFTRESET_NUMB                                                          1
#define            DUALMODETIMER2_TIOCP_CFG_16_0_SOFTRESET_RES_VAL                                                       0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_16_0_AUTOIDLE_POS                                                            0
#define            DUALMODETIMER2_TIOCP_CFG_16_0_AUTOIDLE_NUMB                                                           1
#define            DUALMODETIMER2_TIOCP_CFG_16_0_AUTOIDLE_RES_VAL                                                        0x0
//R/W



#ifndef DSP_ACCESS
#define            DUALMODETIMER2_TIOCP_CFG_16_2                                                                       REG16(DUALMODETIMER2_BASE_ADDR_ARM+DUALMODETIMER2_TIOCP_CFG_OFFSET*coeff16_arm+2)
#else
#define            DUALMODETIMER2_TIOCP_CFG_16_2                                                                       REG16(DUALMODETIMER2_BASE_ADDR_DSP+DUALMODETIMER2_TIOCP_CFG_OFFSET+1)
#endif


#define            DUALMODETIMER2_TIOCP_CFG_16_2_EMUFREE_POS                                                             5
#define            DUALMODETIMER2_TIOCP_CFG_16_2_EMUFREE_NUMB                                                            1
#define            DUALMODETIMER2_TIOCP_CFG_16_2_EMUFREE_RES_VAL                                                         0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_16_2_IDLEMODE_POS                                                            3
#define            DUALMODETIMER2_TIOCP_CFG_16_2_IDLEMODE_NUMB                                                           2
#define            DUALMODETIMER2_TIOCP_CFG_16_2_IDLEMODE_RES_VAL                                                        0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_16_2_ENAWAKEUP_POS                                                           2
#define            DUALMODETIMER2_TIOCP_CFG_16_2_ENAWAKEUP_NUMB                                                          1
#define            DUALMODETIMER2_TIOCP_CFG_16_2_ENAWAKEUP_RES_VAL                                                       0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_16_2_SOFTRESET_POS                                                           1
#define            DUALMODETIMER2_TIOCP_CFG_16_2_SOFTRESET_NUMB                                                          1
#define            DUALMODETIMER2_TIOCP_CFG_16_2_SOFTRESET_RES_VAL                                                       0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_16_2_AUTOIDLE_POS                                                            0
#define            DUALMODETIMER2_TIOCP_CFG_16_2_AUTOIDLE_NUMB                                                           1
#define            DUALMODETIMER2_TIOCP_CFG_16_2_AUTOIDLE_RES_VAL                                                        0x0

#ifndef DSP_ACCESS

#define            DUALMODETIMER2_TIOCP_CFG_32                                                                         REG32(DUALMODETIMER2_BASE_ADDR_ARM+DUALMODETIMER2_TIOCP_CFG_OFFSET*coeff32_arm)


#define            DUALMODETIMER2_TIOCP_CFG_32_EMUFREE_POS                                                               5
#define            DUALMODETIMER2_TIOCP_CFG_32_EMUFREE_NUMB                                                              1
#define            DUALMODETIMER2_TIOCP_CFG_32_EMUFREE_RES_VAL                                                           0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_32_IDLEMODE_POS                                                              3
#define            DUALMODETIMER2_TIOCP_CFG_32_IDLEMODE_NUMB                                                             2
#define            DUALMODETIMER2_TIOCP_CFG_32_IDLEMODE_RES_VAL                                                          0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_32_ENAWAKEUP_POS                                                             2
#define            DUALMODETIMER2_TIOCP_CFG_32_ENAWAKEUP_NUMB                                                            1
#define            DUALMODETIMER2_TIOCP_CFG_32_ENAWAKEUP_RES_VAL                                                         0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_32_SOFTRESET_POS                                                             1
#define            DUALMODETIMER2_TIOCP_CFG_32_SOFTRESET_NUMB                                                            1
#define            DUALMODETIMER2_TIOCP_CFG_32_SOFTRESET_RES_VAL                                                         0x0
//R/W

#define            DUALMODETIMER2_TIOCP_CFG_32_AUTOIDLE_POS                                                              0
#define            DUALMODETIMER2_TIOCP_CFG_32_AUTOIDLE_NUMB                                                             1
#define            DUALMODETIMER2_TIOCP_CFG_32_AUTOIDLE_RES_VAL                                                          0x0