arminth_l21.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :arminth_l21.h
//
//   Date of Module Modification:6/11/01
//   Date of Generation :3/20/02
//
//
//========================================================================
#include "mapping.h"
#ifndef _ARMINTH_L21__H
#define _ARMINTH_L21__H

//BEGIN INC GENERATION
//--------------------------------------


//Register Offset
//-------------------
#define            ARMINTH_L21_ITR_OFFSET                                                                              0x00
#define            ARMINTH_L21_MIR_OFFSET                                                                              0x04
#define            ARMINTH_L21_SIR_IRQ_CODE_OFFSET                                                                     0x10
#define            ARMINTH_L21_SIR_FIQ_CODE_OFFSET                                                                     0x14
#define            ARMINTH_L21_CONTROL_REG_OFFSET                                                                      0x18
#define            ARMINTH_L21_ILRX_OFFSET                                                                             0x1C
#define            ARMINTH_L21_ISR_OFFSET                                                                              0x9C




//ARMINTH_L21_ITR
//-------------------
#define            ARMINTH_L21_ITR                                                                                     REG32(ARMINTH_L21_BASE_ADDR_ARM+ARMINTH_L21_ITR_OFFSET)


#define            ARMINTH_L21_ITR_ACT_IRQ_POS                                                                           0
#define            ARMINTH_L21_ITR_ACT_IRQ_NUMB                                                                          32
#define            ARMINTH_L21_ITR_ACT_IRQ_RES_VAL                                                                       0x0000
//R/W


//ARMINTH_L21_MIR
//-------------------
#define            ARMINTH_L21_MIR                                                                                     REG32(ARMINTH_L21_BASE_ADDR_ARM+ARMINTH_L21_MIR_OFFSET)


#define            ARMINTH_L21_MIR_IRQ_MSK_POS                                                                           0
#define            ARMINTH_L21_MIR_IRQ_MSK_NUMB                                                                          32
#define            ARMINTH_L21_MIR_IRQ_MSK_RES_VAL                                                                       0xFFFF
//R/W


//ARMINTH_L21_SIR_IRQ_CODE
//-------------------
#define            ARMINTH_L21_SIR_IRQ_CODE                                                                            REG32(ARMINTH_L21_BASE_ADDR_ARM+ARMINTH_L21_SIR_IRQ_CODE_OFFSET)


#define            ARMINTH_L21_SIR_IRQ_CODE_RESERVED_POS                                                                 5
#define            ARMINTH_L21_SIR_IRQ_CODE_RESERVED_NUMB                                                                27
#define            ARMINTH_L21_SIR_IRQ_CODE_RESERVED_RES_VAL                                                             0x0
//R/W

#define            ARMINTH_L21_SIR_IRQ_CODE_IRQ_NUM_POS                                                                  0
#define            ARMINTH_L21_SIR_IRQ_CODE_IRQ_NUM_NUMB                                                                 5
#define            ARMINTH_L21_SIR_IRQ_CODE_IRQ_NUM_RES_VAL                                                              0x0
//R


//ARMINTH_L21_SIR_FIQ_CODE
//-------------------
#define            ARMINTH_L21_SIR_FIQ_CODE                                                                            REG32(ARMINTH_L21_BASE_ADDR_ARM+ARMINTH_L21_SIR_FIQ_CODE_OFFSET)


#define            ARMINTH_L21_SIR_FIQ_CODE_RESERVED_POS                                                                 5
#define            ARMINTH_L21_SIR_FIQ_CODE_RESERVED_NUMB                                                                27
#define            ARMINTH_L21_SIR_FIQ_CODE_RESERVED_RES_VAL                                                             0x0
//R/W

#define            ARMINTH_L21_SIR_FIQ_CODE_FIQ_NUM_POS                                                                  0
#define            ARMINTH_L21_SIR_FIQ_CODE_FIQ_NUM_NUMB                                                                 5
#define            ARMINTH_L21_SIR_FIQ_CODE_FIQ_NUM_RES_VAL                                                              0x0
//R


//ARMINTH_L21_CONTROL_REG
//-------------------
#define            ARMINTH_L21_CONTROL_REG                                                                             REG32(ARMINTH_L21_BASE_ADDR_ARM+ARMINTH_L21_CONTROL_REG_OFFSET)


#define            ARMINTH_L21_CONTROL_REG_RESERVED_POS                                                                  2
#define            ARMINTH_L21_CONTROL_REG_RESERVED_NUMB                                                                 30
#define            ARMINTH_L21_CONTROL_REG_RESERVED_RES_VAL                                                              0x0
//R/W

#define            ARMINTH_L21_CONTROL_REG_NEW_FIQ_AGR_POS                                                               1
#define            ARMINTH_L21_CONTROL_REG_NEW_FIQ_AGR_NUMB                                                              1
#define            ARMINTH_L21_CONTROL_REG_NEW_FIQ_AGR_RES_VAL                                                           0x0
//R/W

#define            ARMINTH_L21_CONTROL_REG_NEW_IRQ_AGR_POS                                                               0
#define            ARMINTH_L21_CONTROL_REG_NEW_IRQ_AGR_NUMB                                                              1
#define            ARMINTH_L21_CONTROL_REG_NEW_IRQ_AGR_RES_VAL                                                           0x0
//R/W


//ARMINTH_L21_ILRX
//-------------------
#define            ARMINTH_L21_ILRX                                                                                    REG32(ARMINTH_L21_BASE_ADDR_ARM+ARMINTH_L21_ILRX_OFFSET)


#define            ARMINTH_L21_ILRX_RESERVED_POS                                                                         7
#define            ARMINTH_L21_ILRX_RESERVED_NUMB                                                                        25
#define            ARMINTH_L21_ILRX_RESERVED_RES_VAL                                                                     0x0
//R/W

#define            ARMINTH_L21_ILRX_PRIORITY_POS                                                                         2
#define            ARMINTH_L21_ILRX_PRIORITY_NUMB                                                                        5
#define            ARMINTH_L21_ILRX_PRIORITY_RES_VAL                                                                     0x0
//R/W

#define            ARMINTH_L21_ILRX_SENS_EDGE_POS                                                                        1
#define            ARMINTH_L21_ILRX_SENS_EDGE_NUMB                                                                       1
#define            ARMINTH_L21_ILRX_SENS_EDGE_RES_VAL                                                                    0x0
//R/W

#define            ARMINTH_L21_ILRX_FIQ_POS                                                                              0
#define            ARMINTH_L21_ILRX_FIQ_NUMB                                                                             1
#define            ARMINTH_L21_ILRX_FIQ_RES_VAL                                                                          0x0
//R/W


//ARMINTH_L21_ISR
//-------------------
#define            ARMINTH_L21_ISR                                                                                     REG32(ARMINTH_L21_BASE_ADDR_ARM+ARMINTH_L21_ISR_OFFSET)


#define            ARMINTH_L21_ISR_SISR_POS                                                                              0
#define            ARMINTH_L21_ISR_SISR_NUMB                                                                             32
#define            ARMINTH_L21_ISR_SISR_RES_VAL                                                                          0x0
//R/W

#endif