wcdma_ccp.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//Task_Request_Bits_2
//-------------------------
#define            Task_Request_Bits_2                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Task_Request_Bits_2_OFFSET) << 2))
#define            Task_Request_Bits_2_RES_VAL                0x00000000
//R/W
//-------------------------



//Task_Request_Bits_3
//-------------------------
#define            Task_Request_Bits_3                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Task_Request_Bits_3_OFFSET) << 2))
#define            Task_Request_Bits_3_RES_VAL                0x00000000
//R/W
//-------------------------



//Task_Update_Cycle
//-------------------------
#define            Task_Update_Cycle                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Task_Update_Cycle_OFFSET) << 2))
#define            Task_Update_Cycle_RES_VAL                0x00000003
//R/W
//-------------------------



//PSC_Register
//-------------------------
#define            PSC_Register                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+PSC_Register_OFFSET) << 2))
#define            PSC_Register_RES_VAL                0x6AC0
//R/W
//-------------------------



//SSC_Register
//-------------------------
#define            SSC_Register                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+SSC_Register_OFFSET) << 2))
#define            SSC_Register_RES_VAL                0x95C0
//R/W
//-------------------------



//Search_Code_Symbol_Location
//-------------------------
#define            Search_Code_Symbol_Location                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Search_Code_Symbol_Location_OFFSET) << 2))
#define            Search_Code_Symbol_Location_RES_VAL                0x00000000
//R/W
//-------------------------



//Dedicated_Pilots_Start_Addr
//-------------------------
#define            Dedicated_Pilots_Start_Addr                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Dedicated_Pilots_Start_Addr_OFFSET) << 2))
#define            Dedicated_Pilots_Start_Addr_RES_VAL                0x00000000
//R/W
//-------------------------



//TPC_Start_Addr
//-------------------------
#define            TPC_Start_Addr                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+TPC_Start_Addr_OFFSET) << 2))
#define            TPC_Start_Addr_RES_VAL                0x00000000
//R/W
//-------------------------



//EOL_Slot_Mask_0
//-------------------------
#define            EOL_Slot_Mask_0                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+EOL_Slot_Mask_0_OFFSET) << 2))
#define            EOL_Slot_Mask_0_RES_VAL                0x00000000
//R/W
//-------------------------



//EOL_Slot_Mask_1
//-------------------------
#define            EOL_Slot_Mask_1                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+EOL_Slot_Mask_1_OFFSET) << 2))
#define            EOL_Slot_Mask_1_RES_VAL                0x00000000
//R/W
//-------------------------



//EOL_Slot_Mask_2
//-------------------------
#define            EOL_Slot_Mask_2                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+EOL_Slot_Mask_2_OFFSET) << 2))
#define            EOL_Slot_Mask_2_RES_VAL                0x00000000
//R/W
//-------------------------



//EOL_Slot_Mask_3
//-------------------------
#define            EOL_Slot_Mask_3                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+EOL_Slot_Mask_3_OFFSET) << 2))
#define            EOL_Slot_Mask_3_RES_VAL                0x00000000
//R/W
//-------------------------



//EOL_Slot_Mask_4
//-------------------------
#define            EOL_Slot_Mask_4                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+EOL_Slot_Mask_4_OFFSET) << 2))
#define            EOL_Slot_Mask_4_RES_VAL                0x00000000
//R/W
//-------------------------



//EOL_Slot_Mask_5
//-------------------------
#define            EOL_Slot_Mask_5                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+EOL_Slot_Mask_5_OFFSET) << 2))
#define            EOL_Slot_Mask_5_RES_VAL                0x00000000
//R/W
//-------------------------



//Long_Code_Test_I
//-------------------------
#define            Long_Code_Test_I                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Long_Code_Test_I_OFFSET) << 2))
#define            Long_Code_Test_I_RES_VAL                0x00000000
//R/W
//-------------------------



//Long_Code_Test_Q
//-------------------------
#define            Long_Code_Test_Q                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Long_Code_Test_Q_OFFSET) << 2))
#define            Long_Code_Test_Q_RES_VAL                0x00000000
//R/W
//-------------------------



//Long_Code_Test_Enable
//-------------------------
#define            Long_Code_Test_Enable                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Long_Code_Test_Enable_OFFSET) << 2))
#define            Long_Code_Test_Enable_RES_VAL                0x00000000
//R/W
//-------------------------



//Walsh_Code_Test
//-------------------------
#define            Walsh_Code_Test                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Walsh_Code_Test_OFFSET) << 2))
#define            Walsh_Code_Test_RES_VAL                0x00000000
//R/W
//-------------------------



//Walsh_Code_Test_Enable
//-------------------------
#define            Walsh_Code_Test_Enable                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Walsh_Code_Test_Enable_OFFSET) << 2))
#define            Walsh_Code_Test_Enable_RES_VAL                0x00000000
//R/W
//-------------------------



//PMT_Select
//-------------------------
#define            PMT_Select                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+PMT_Select_OFFSET) << 2))
#define            PMT_Select_RES_VAL                0x00000000
//R/W
//-------------------------



//CCP_Test_Ctrl
//-------------------------
#define            CCP_Test_Ctrl                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+CCP_Test_Ctrl_OFFSET) << 2))
#define            CCP_Test_Ctrl_RES_VAL                0x00000000
//R/W
//-------------------------



//Clock_Definition
//-------------------------
#define            Clock_Definition                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Clock_Definition_OFFSET) << 2))
#define            Clock_Definition_RES_VAL                0x00000000
//R/W
//-------------------------



//Version_ID
//-------------------------
#define            Version_ID                        REG32(WCDMA_CS_LB+((WCDMA_CCP_BASE_ADDR+Version_ID_OFFSET) << 2))
#define            Version_ID_RES_VAL                0x
//R/W
//No write to this reg are allowed
//-------------------------







#define             CCP_status_RD_MASK    0x00000003
//The CCP_status reg has no write-able bits


#define             run_stop_status_0_RD_MASK    0xFFFF
//The run_stop_status_0 reg has no write-able bits


#define             run_stop_status_1_RD_MASK    0xFFFF
//The run_stop_status_1 reg has no write-able bits


#define             run_stop_status_2_RD_MASK    0xFFFF
//The run_stop_status_2 reg has no write-able bits


#define             run_stop_status_3_RD_MASK    0xFFFF
//The run_stop_status_3 reg has no write-able bits


#define             run_stop_status_4_RD_MASK    0xFFFF
//The run_stop_status_4 reg has no write-able bits


#define             run_stop_status_5_RD_MASK    0xFFFF
//The run_stop_status_5 reg has no write-able bits


#define             run_stop_status_6_RD_MASK    0xFFFF
//The run_stop_status_6 reg has no write-able bits


#define             run_stop_status_7_RD_MASK    0xFFFF
//The run_stop_status_7 reg has no write-able bits


#define             ping_pong_status_0_RD_MASK    0xFFFF
//The ping_pong_status_0 reg has no write-able bits


#define             ping_pong_status_1_RD_MASK    0xFFFF
//The ping_pong_status_1 reg has no write-able bits


#define             ping_pong_status_2_RD_MASK    0xFFFF
//The ping_pong_status_2 reg has no write-able bits


#define             ping_pong_status_3_RD_MASK    0xFFFF
//The ping_pong_status_3 reg has no write-able bits


#define             ping_pong_status_4_RD_MASK    0xFFFF
//The ping_pong_status_4 reg has no write-able bits


#define             ping_pong_status_5_RD_MASK    0xFFFF
//The ping_pong_status_5 reg has no write-able bits


#define             ping_pong_status_6_RD_MASK    0xFFFF
//The ping_pong_status_6 reg has no write-able bits


#define             ping_pong_status_7_RD_MASK    0xFFFF
//The ping_pong_status_7 reg has no write-able bits


#define             task_command_0_RD_MASK    0xFFFF
//The task_command_0 reg has no write-able bits


#define             task_command_1_RD_MASK    0xFFFF
//The task_command_1 reg has no write-able bits


#define             task_command_2_RD_MASK    0xFFFF
//The task_command_2 reg has no write-able bits


#define             task_command_3_RD_MASK    0xFFFF
//The task_command_3 reg has no write-able bits


#define             FIFO_0_status_RD_MASK    0x1F
//The FIFO_0_status reg has no write-able bits


#define             FIFO_1_status_RD_MASK    0x1F
//The FIFO_1_status reg has no write-able bits


#define             FIFO_2_status_RD_MASK    0x1F
//The FIFO_2_status reg has no write-able bits


#define             FIFO_3_status_RD_MASK    0x1F
//The FIFO_3_status reg has no write-able bits


#define             Cycle_Count_RD_MASK    0x1FF
//The Cycle_Count reg has no write-able bits


#define             Task_Update_Time_Stamp_RD_MASK    0xFFFF
//The Task_Update_Time_Stamp reg has no write-able bits


#define             Interrupt_Error_Event_Status_RD_MASK    0x3F
//The Interrupt_Error_Event_Status reg has no write-able bits


#define             Interrupt_System_Event_Status_RD_MASK    0x00000001
//The Interrupt_System_Event_Status reg has no write-able bits


#define             Task_Request_Bits_0_RD_MASK    0xFFFF

#define             Task_Request_Bits_0_WR_MASK    0xFFFF


#define             Task_Request_Bits_1_RD_MASK    0xFFFF

#define             Task_Request_Bits_1_WR_MASK    0xFFFF


#define             Task_Request_Bits_2_RD_MASK    0xFFFF

#define             Task_Request_Bits_2_WR_MASK    0xFFFF


#define             Task_Request_Bits_3_RD_MASK    0xFFFF

#define             Task_Request_Bits_3_WR_MASK    0xFFFF


#define             Task_Update_Cycle_RD_MASK    0x0FF

#define             Task_Update_Cycle_WR_MASK    0x0FF


#define             PSC_Register_RD_MASK    0xFFFF

#define             PSC_Register_WR_MASK    0xFFFF


#define             SSC_Register_RD_MASK    0xFFFF

#define             SSC_Register_WR_MASK    0xFFFF


#define             Search_Code_Symbol_Location_RD_MASK    0x000F

#define             Search_Code_Symbol_Location_WR_MASK    0x000F


#define             Dedicated_Pilots_Start_Addr_RD_MASK    0x3fff

#define             Dedicated_Pilots_Start_Addr_WR_MASK    0x3fff


#define             TPC_Start_Addr_RD_MASK    0x3fff

#define             TPC_Start_Addr_WR_MASK    0x3fff


#define             EOL_Slot_Mask_0_RD_MASK    0x7FFF

#define             EOL_Slot_Mask_0_WR_MASK    0x7FFF


#define             EOL_Slot_Mask_1_RD_MASK    0x7FFF

#define             EOL_Slot_Mask_1_WR_MASK    0x7FFF