📄 led_bootled.h
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/*==============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments. For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 2002, (C) Copyright 2002 Texas Instruments. All rights reserved.
//
// Created : 5th of September, 2002, 2.00pm
//
// Filename : hel2_bootled_led.h
//
// Description : Header file for boot LED ARM926EJS assembler programs
//
// Project : HELEN2, OMAP1610
//
// Author : Dayo Adeyeye
//
// FUNCTIONS PROVIDED :
//
//
============================================================================= */
#ifndef _LED_BOOTLED__HH
#define _LED_BOOTLED__HH
#include "global_types.h"
#define MASK_L_16 0x0000FFFF
#define MASK_U_16 0xFFFF0000
#define CLKRST_DPLLCTL1_REG REG16(0xFFFECF00)
#define CLKRST_DPLLCTL2_REG REG16(0xFFFED000)
#define ARM_CKCTL_REG REG16(0xFFFECE00)
#define ARM_IDLECT1_REG REG16(0xFFFECE04)
#define ARM_IDLECT2_REG REG16(0xFFFECE08)
#define ARM_EWUPCT_REG REG16(0xFFFECE0C)
#define ARM_RSTCT1_REG REG16(0xFFFECE10)
#define ARM_RSTCT2_REG REG16(0xFFFECE14)
#define ARM_SYSST_REG REG16(0xFFFECE18)
#define ARM_CKOUT1_REG REG16(0xFFFECE1C)
#define ARM_CKOUT2_REG REG16(0xFFFECE20)
#define ARM_IDLECT3_REG REG16(0xFFFECE24)
#define DSP_CKCTL_ADDR REG16(0xE1008000)
#define DSP_IDLECT1_ADDR REG16(0xE1008004)
#define DSP_IDLECT2_ADDR REG16(0xE1008008)
#define DSP_EWUPCT_ADDR REG16(0xE100800C) // reserved
#define DSP_RSTCT1_ADDR REG16(0xE1008010) // reserved
#define DSP_RSTCT2_ADDR REG16(0xE1008014)
#define DSP_SYSST_ADDR REG16(0xE1008018)
#define DSP_CKOUT1_ADDR REG16(0xE100801C) // reserved
#define DSP_CKOUT2_ADDR REG16(0xE1008020) // reserved
// internal EMIFS cs memory map
#define NSBOOTROM_BASE_ADDR 0x00000000
#define SECUREROM_ENTRY_PT_ADDR 0x00003C18
#define SECUREROM_START_ADDR 0x00004080
#define SECUREROM_END_ADDR 0x0000FFFF // 64KBytes
#define SECRAM_BASE_ADDR 0x00200000
#define SECRAM_END_ADDR 0x00203FFF // 16KBytes
#define SECFUSE_BASE_ADDR 0x00210000
// external EMIFS cs and NOR Flash memory map
#define NRFLASH_BASE_ADDR 0x02000000
#define CS0_BASE_ADDR 0x00000000
#define CS1_BASE_ADDR 0x04000000
#define CS2_BASE_ADDR 0x08000000
#define CS3_BASE_ADDR 0x0c000000
// external EMIFF memory map
#define SDRAM_BASE_ADDR 0x10000000
// internal OCP T1 SRAM memory map location
#define TSTSRAM_BASE_ADDR 0x20000000
#define TSTSRAM_END_ADDR 0x20003FFF // 16KBytes
// DSP API Memory Space Map
#define DARAM_TOP_ADDR 0xE0000000 // 8 x 8Kbytes = 8 * 0x2000
#define DARAM_BOTTOM_ADDR 0xE000FFFF // 64Kbytes
#define SARAM_TOP_ADDR 0xE0010000 // 12 x 8Kbytes = 12 * 0x2000
#define SARAM_BOTTOM_ADDR 0xE0027FFF // 96Kbytes
#define SARAM0_BASE_ADDR 0xE0010000 // 8Kbytes = 0 * 0x2000
#define SARAM1_BASE_ADDR 0xE0012000 // 8Kbytes = 1 * 0x2000
#define SARAM2_BASE_ADDR 0xE0014000 // 8Kbytes = 2 * 0x2000
#define SARAM3_BASE_ADDR 0xE0016000 // 8Kbytes = 3 * 0x2000
#define SARAM4_BASE_ADDR 0xE0018000 // 8Kbytes = 4 * 0x2000
#define SARAM5_BASE_ADDR 0xE001A000 // 8Kbytes = 5 * 0x2000
#define SARAM6_BASE_ADDR 0xE001C000 // 8Kbytes = 6 * 0x2000
#define SARAM7_BASE_ADDR 0xE001E000 // 8Kbytes = 7 * 0x2000
#define SARAM8_BASE_ADDR 0xE0020000 // 8Kbytes = 8 * 0x2000
#define SARAM9_BASE_ADDR 0xE0022000 // 8Kbytes = 9 * 0x2000
#define SARAMA_BASE_ADDR 0xE0024000 // 8Kbytes = A * 0x2000
#define SARAMB_BASE_ADDR 0xE0026000 // 8Kbytes = B * 0x2000
#define CLKM2_BASE_ADDR 0xE1008000
#define GPIO1_BASE_ADDR_DSP 0xE101E400
#define GPIO2_BASE_ADDR_DSP 0xE101EC00
#define GPIO3_BASE_ADDR_DSP 0xE101B400
#define GPIO4_BASE_ADDR_DSP 0xE101BC00
#define DSPMBX_BASE_ADDR 0xE101F000
// EMIFS_CFG //R/W
#define EMIFS_CFG_REG REG32(0xFFFECC0C)
// EMIFS_CS_CFG_(0)(1)(2)(3) //R/W
#define EMIFS_CS_CFG_0_REG REG32(0xFFFECC00)
#define EMIFS_CS_CFG_1_REG REG32(0xFFFECC14)
#define EMIFS_CS_CFG_2_REG REG32(0xFFFECC18)
#define EMIFS_CS_CFG_3_REG REG32(0xFFFECC1C)
#define CTE_Array_Add 0x0C00FFC0 // External CS3 memory for CTE values
#define CTE_Space_RAM 0x20000004 // 4(TLB)+60Bytes(CTE)+256Bytes(Spy) in TestSRAM
#define SPY_SRAM_ADDR 0x20000040
// CTE Mapping, 32 x 16bits = 64bytes
#define CTE_ARM9_SRC_SIZE_LSB REG16(CTE_Space_RAM+0)
#define CTE_ARM9_SRC_SIZE_MSB REG16(CTE_Space_RAM+2)
#define CTE_LEAD3_SRC_SIZE_LSB REG16(CTE_Space_RAM+4)
#define CTE_LEAD3_SRC_SIZE_MSB REG16(CTE_Space_RAM+6)
#define CTE_DPLL1_BYPASS_VALUE REG16(CTE_Space_RAM+8)
#define CTE_ARM_CLK_CONTROL REG16(CTE_Space_RAM+10)
#define CTE_SYNC_BYPASS_MODE REG16(CTE_Space_RAM+12)
#define CTE_LDO_STDY_BYPASS REG16(CTE_Space_RAM+14)
#define CTE_SYNC_INTSRC_TESTCASE REG16(CTE_Space_RAM+16)
#define CTE_WAKE_INTSRC_TESTCASE REG16(CTE_Space_RAM+18)
#define CTE_GPIO_ADDR_LSB REG16(CTE_Space_RAM+20)
#define CTE_GPIO_ADDR_MSB REG16(CTE_Space_RAM+22)
#define CTE_GPIO_SYNC_PIN REG16(CTE_Space_RAM+24)
#define CTE_GPIO_EXEC_PIN REG16(CTE_Space_RAM+26)
#define CTE_GPIO_STAT_PIN REG16(CTE_Space_RAM+28)
#define CTE_EMIFS_CONFIG_CTRL REG16(CTE_Space_RAM+30)
#define CTE_DPLL_TIMEOUT_VALUE REG16(CTE_Space_RAM+32)
#define CTE_ULPD_TIMEOUT_VALUE REG16(CTE_Space_RAM+34)
#define CTE_EXEC_TIMEOUT_VALUE REG16(CTE_Space_RAM+36)
#define CTE_20 REG16(CTE_Space_RAM+38)
#define CTE_21 REG16(CTE_Space_RAM+40)
extern void INT_EndOfLoad(UWORD32 gpio_base_addr,
UWORD16 execpin,
UWORD16 syncpin,
UWORD16 ledtimeout);
extern void StartDMA_sleep(UWORD32 gpio_base_addr,
UWORD16 execpin);
extern void IOCONF(void);
extern void BootStop_LED(UWORD16 ledsig);
//------------------------------------------------------------------------------
// NAME : RES_Exception_LED(void)
// DESCRIPTION : CPU Exception occured, combined test exception handler
// PARAMETERS : Input : None
// Output: None
// RETURN VALUE: None
// LIMITATIONS : None
//------------------------------------------------------------------------------
void led_boot_init(void);
#endif /* _HEL2_COMMON_ASM_LED__HH */
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